lrs1386 Sharp Microelectronics of the Americas, lrs1386 Datasheet - Page 61

• Manufacturer Part Number: lrs1386
• Description: Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

3 Bus Operation
The system CPU reads and writes the flash memory. All
bus cycles to or from the flash memory conform to
standard microprocessor bus cycles. Table 4 lists the bus
operation.
3.1 Read Array
LH28F320BX/LH28F640BX series has seven control
pins (CLK, CE#, OE#, ADV#, WE#, RST# and WP#).
When RST# is V
array, status register, identifier codes, OTP block and
query codes independent of the voltage on V
The device is automatically initialized upon power-up or
device reset mode and set to asynchronous read mode in
which 8-word page mode is available. As necessary, write
the appropriate read command (Read Array, Read
Identifier codes/OTP, Read Query or Read Status Register
command) with the partition address to the CUI
(Command User Interface). The CUI decodes the
partition address and set the target partition to the
appropriate read mode.
Synchronous burst mode can be set by writing the Set
Read Configuration Register command. It is impossible
to set one partition to asynchronous read mode and other
partition to synchronous burst mode at a time.
Asynchronous page mode and synchronous burst mode
are available only for main array, that is, parameter blocks
and main blocks. Read operations for status register,
identifier codes, OTP block and query codes support
single asynchronous read cycle or single synchronous
read cycle.
To read data from the LH28F320BX/LH28F640BX
series, RST# and WE# must be at V
at V
the device selection control, and CE#-low enables the
selected memory device. OE# is the data output (DQ
DQ
data onto the I/O bus.
3.2 Output Disable
With OE# at V
pins DQ
state.
15
IL
) control and OE#-low drives the selected memory
. ADV# must be driven V
0
- DQ
15
IH
, the device outputs are disabled. Output
are placed in a high-impedance (High Z)
IH
, read operations access the memory
Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13302
IL
to fetch address. CE# is
IH
, and CE# and OE#
PP
.
FUM00701
0
-
Model No.: LRS1386
3.3 Standby
CE# at a logic-high level (V
LH28F640BX series in standby mode.
In standby mode, the LH28F320BX/LH28F640BX series
substantially reduces its power consumption because
almost of all internal circuits are inactive. DQ
outputs a High Z state independent of OE#. Even if CE#
is set to V
buffer) program or OTP program, the device continues
the operation and consumes active power until the
completion of the operation.
3.4 Reset
Driving RST# to logic-low level (V
LH28F320BX/LH28F640BX series in reset mode.
If RST# is held V
the device is deselected and internal circuitry is turned
off. Outputs are placed in a High Z state. Status register is
set to 80H. Time t
mode until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
device returns to the initial mode described in Section 2.1.
During block erase, full chip erase, (page buffer) program
or OTP program mode, RST#-low will abort the
operation. Memory contents being altered are no longer
valid; the data may be partially erased or programmed.
Status register bit SR.7 remains "0" until the reset
operation has been completed. After RST# goes to V
time t
command can be written.
As with any automated device, it is important to assert
RST# during system reset. When the system comes out of
reset, it expects to read the data from the flash memory.
LH28F320BX/LH28F640BX series allows proper CPU
initialization following a system reset through the use of
the RST# input. In this application, RST# is controlled by
the same RESET# signal that resets the system CPU.
After return from reset mode, the LH28F320BX/
LH28F640BX series is automatically set to asynchronous
read mode in which 8-word page mode is available. Delay
time t
valid.
PHQV
PHWL
IH
is required until memory access outputs are
during block erase, full chip erase, (page
and t
March 2, 2001
IL
PHQV
for a minimum t
PHEL
is required after return from reset
is required before another
IH
) places the LH28F320BX/
PLPH
IL
in read modes,
) places the
Rev. 2.20
0
15
-DQ
IH
15
,