lrs1386 Sharp Microelectronics of the Americas, lrs1386 Datasheet - Page 48

• Manufacturer Part Number: lrs1386
• Description: Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

1 Introduction
This appendix describes how to use the LH28F320BX/
LH28F640BX series, Synchronous/Page Mode Dual
Work
LH28F320BX/LH28F640BX series. Sections 2, 3, 4 and
5 describe the memory organization and functionality.
When designing a specific system, take into design
considerations described in Section 5.
1.1 Features
Synchronous/Page Mode Dual Work Flash memory
LH28F320BX/LH28F640BX series has the following
features:
1.2 Definition of Block, Plane and Partition
Block, Plane and Partition are defined and used in this
document as explained below.
• Dual work operation
• Flexible partition configuration
• High performance asynchronous reads and
• Page buffer program
• Individual block locking and all blocks locked on
• 8-word OTP (One Time Program) block
• Low power consumption
• Parameter block architecture
• Block
• Plane: 32M-bit and 64M-bit devices are divided into
• Partition: Read operation can be done in one partition
synchronous burst reads
power-up
Main Block: 32K Words.
Parameter Block: 4K Words.
32M-bit device has 8 parameter blocks and 63 main
blocks.
64M-bit device has 8 parameter blocks and 127 main
blocks.
four physical planes (see Table 1).
Plane0 or Plane3 contains parameter blocks and main
blocks. Plane1 and Plane2 consist of only main
blocks.
while Program/Erase operation is being done in
another partition. Partition contains at least one plane
or up to four planes. Partition boundaries can be
flexibly set to any plane boundary by the Set Partition
Configuration Register command. If the partition
configuration register is set to "111" (4 plane dual
work mode), the partition is exactly the same as a
plane. See Section 4.17 for more information.
Flash
memory.
Synchronous burst mode will be available for future device.
Section
Appendix to Spec No.: MFM2-J13302
1
outlines
FUM00701
the
Model No.: LRS1386
1.3 Product Overview
Synchronous/Page Mode Dual Work Flash memory
LH28F320BX/LH28F640BX series is capable of dual
work operation: erase or program operation on one
partition and read operation on other partitions (see Table
2). The partition to be accessed is automatically identified
according to the input address. Dual work operations can
be achieved by dividing the memory array into four
physical planes as shown in Figure 2.1 through Figure
3.2. Each plane is exactly one quarter of the entire
memory array. The device has also virtual partitions.
Several planes can be flexibly merged to one partition by
writing
command. This feature allows the user to read from one
partition even though one of the other partitions is
executing an erase or program operation. If the device is
set to the 4 partitions configuration, each partition is
exactly the same as each physical plane. After power-up
or device reset, plane 0-2 are merged into one partition for
top parameter devices and plane1-3 are merged into one
partition for bottom parameter devices.
During dual work operation, read operations to the
partition being erased or programmed access the status
register which indicates whether the erase or program
operation is successfully completed or not. Dual work
operation cannot be executed during full chip erase and
OTP program mode.
Memory array data can be read in two ways, that is,
asynchronous 8-word page mode or synchronous burst
mode. The default after power-up or device reset is the
asynchronous read mode in which 8-word page mode is
available. The user must set the read configuration
register to enable the synchronous burst mode by writing
the Set Read Configuration Register command. CLK is
then used to increment the internal burst address
generator, synchronize with the host, and deliver data
every clock cycle. The WAIT# output pin is used to signal
Plane #
Plane 0
Plane 1
Plane 2
Plane 3
Table 1. Address Range of Each Plane
the
000000H-07FFFFH
080000H-0FFFFFH
100000H-17FFFFH
180000H-1FFFFFH
Contains the Blocks within the following
Set
March 2, 2001
32M bit
Partition
Address
Configuration
000000H-0FFFFFH
100000H-1FFFFFH
200000H-2FFFFFH
300000H-3FFFFFH
64M bit
Rev. 2.20
Register
2