lrs1386 Sharp Microelectronics of the Americas, lrs1386 Datasheet - Page 54

• Manufacturer Part Number: lrs1386
• Description: Flash Memory
• Manufacturer: Sharp Microelectronics of the Americas

1.4 Product Description
1.4.1 Memory Block Organization
The device is divided into four physical planes and the
partitions can be flexibly configured by the Set Partition
Configuration Register command. This allows dual work
operations, that is, simultaneous read-while-erase and
read-while-program operations. For the address locations
of the blocks, see the memory map in Figure 2.1 through
Figure 3.2.
1.4.2 Four Physical Planes
LH28F320BX/LH28F640BX series has four physical
planes (one parameter plane and three uniform planes).
Each plane consists of 8M-bit (32M-bit device) or 16M-
bit (64M-bit device) Flash memory. The parameter plane
consists of eight 4K-word parameter blocks and fifteen
(32M-bit device) or thirty-one (64M-bit device) 32K-
word main blocks. Each uniform plane consists of sixteen
(32M-bit device) or thirty-two (64M-bit device) 32K-
word main blocks. Each block can be erased
independently up to 100,000 times.
1.4.3 Partition
Partition boundaries can be configured by the Set
Partition Configuration Register command. Dual work
operation can be done in two partitions. See partition
configuration in Table 17 and Figure 17 for more detail.
Only one partition can be erased or programmed at a time
and burst reads cannot cross partition boundaries.
Simultaneous operation modes are shown in Table 2.
1.4.4 Parameter Block
Eight 4K-word parameter blocks within the parameter
partition are provided as the memory area to facilitate
storage of frequently update small parameters that would
normally be stored in EEPROM. By using software
techniques, the word-rewrite functionality of EEPROMs
can be emulated. The protection of the parameter block is
controlled using a combination of the V
block lock bit and block lock-down bit.
1.4.5 Main Block
32K-word main blocks can store code and/or data. The
protection of the main block is also controlled using a
combination of the V
block lock-down bit.
PP
, RST#, WP#, block lock bit and
Appendix to Spec No.: MFM2-J13302
PP
, RST#, WP#,
FUM00701
Model No.: LRS1386
1.4.6 OTP (One Time Program) block
The OTP block is a special block that cannot be erased in
order to secure the high system reliability. This 8-word
(128-bit) OTP block is independent of the 32M-bit or
64M-bit memory area. Figure 4 shows the OTP block
address map.
The OTP block is divided into two areas. One is a factory
programmed area where a unique number has been
programmed
programmed area is "READ ONLY" (already locked).
The other is a customer programmable area that can be
available for customers. This customer programmable
area can also be locked. After locking, this customer
programmable area is protected permanently.
The data within the OTP block can be read by the Read
Identifier Codes/OTP command (90H). To return to read
array mode, write the Read Array command (FFH) to the
CUI.
The OTP block bits are programmed by writing the OTP
Program command (C0H) to the CUI. Write the OTP
Program command (C0H) at the 1st command cycle and
then write the address and the data at the 2nd cycle. If the
OTP program operation is failed, the status register bit
SR.4 is set to "1". If the OTP block is locked, the status
register bits SR.4 and SR.1 are set to "1".
The OTP block can be locked using the OTP Program
command (C0H). Write the OTP Program command
(C0H) at the 1st command cycle and then write the data
(FFFDH) to the lock location (80H) at the 2nd cycle.
Read cycle from address (80H) indicates the lockout state
of the OTP block. Bit 0 of address (80H) means the
factory programmed area lock state ("1" is "NOT
LOCKED" and "0" is "LOCKED"). Bit 1 of address
(80H) means the customer programmable lock state. OTP
block lockout state is not reversible. Unlike the main
array block lock configuration, the lock state of the OTP
block is kept unchanged even if the power is turned off or
reset operation is performed.
The OTP Program command is only available for
programming the OTP block. Page buffer program
operations are available for the main array. OTP program
cannot be suspended through the (Page Buffer) Program
Suspend command (described later). Dual work operation
cannot be executed during OTP program.
in
March 2, 2001
SHARP
factory.
This
Rev. 2.20
factory
8