s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 80

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever
comes first.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax–A12 uniquely select any sector.
BA = Address of the bank (WS128J: A22, A21, A20, WS064J: A21, A20, A19) that is being switched to autoselect mode, is in bypass mode, or is
being erased.
SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked.
SBA = sector address block to be protected.
CR = Configuration Register address bits A19–A12.
OW = Address (A7–A0) is (00011010).
PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity.
PWD = Password Data.
PL = Address (A7-A0) is (00001010)
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0.
RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0.
SL = Address (A7-A0) is (00010010)
WD= Write Data. See “Configuration Register” definition for specific write data
WP = Address (A7-A0) is (00000010)
WPE = address(A7-A0) is (01000010)
Notes:
1. See
2.
3.
4.
5.
6.
7.
8.
9.
10. (BA)X0Fh = 2200h (WS128J), (BA)X0Eh = 2218h (WS128J), (BA)X0Fh = 221Eh (WS064J), (BA)X0Eh = 2201h (WS064J)
11. The data is 0000h for an unlocked sector and 0001h for a locked sector
12. DQ15 - DQ8 = 0, DQ7 - Factory Lock Bit (1 = Locked, 0 = Not Locked), DQ6 -Customer Lock Bit (1 = Locked, 0 = Not Locked), DQ5 =
13. The Unlock Bypass command sequence is required prior to this command sequence.
78
PPB
Commands
PPB Lock
Bit
DPB
Password Protection Mode
Locking Bit Program (Notes 21)
Persistent Protection Mode
Locking Bit Program (Notes 21)
All values are in hexadecimal.
Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of
the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1).
Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PD3-PD0.
Unless otherwise noted, address bits Amax–A12 are don’t cares.
Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system
must write the reset command to return the device to reading array data.
No unlock or command cycles required when bank is reading array data.
The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a
bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock.
The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the
Command Sequence
Handshake Bit (1 = Reserved, 0 = Standard Handshake)8, DQ4 & DQ3 - Boot Code (00= Dual Boot Sector, 01= Top Boot Sector, 10=
Bottom Boot Sector, 11=No Boot Sector), DQ2 - DQ0 = 001
Table 11.1
Command Sequence
PPB Program (Notes
21)
All PPB Erase (Notes
22, 24)
PPB Status (Note 25)
PPB Lock Bit Set
PPB Lock Bit Status
DPB Write
DPB Erase
DPB Status
(Note
1)
for description of bus operations.
section for more information.
6
6
4
3
4
4
4
4
6
6
Addr
555
555
555
555
555
555
555
555
555
555
First
Data
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Addr
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
Second
S29WS128J/064J
Data
55
55
55
55
55
55
55
55
55
55
D a t a
(BA)
(BA)
Addr
SBA
555
555
555
555
555
555
555
555
555
555
Third
Data
60
60
90
78
58
48
48
58
60
60
S h e e t
Bus Cycles (Notes 1–6)
+ WP
+WP
WPE
Addr
SBA
SBA
BA
SA
SA
SA
PL
SL
Fourth
Data
(0)
(1)
(0)
RD
RD
RD
68
60
X1
X0
68
68
+ WP
WPE
Addr
SBA
SBA
SL
PL
Fifth
Data
48
40
48
48
Addr
XX
XX
S29WS-J_M0_A4 June 24, 2005
SL
PL
Sixth
Data
RD
(0)
RD
(0)
RD
(0)
RD
(0)
Autoselect
Addr
Seventh
Data