s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 66

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

64
14.2.1
14.2.2
Read Mode Setting
On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting
allows the system to enable or disable burst mode during system operations. Address A19 deter-
mines this setting: “1’ for asynchronous mode, “0” for synchronous mode.
Programmable Wait State Configuration
The programmable wait state feature informs the device of the number of clock cycles that must
elapse after AVD# is driven active before data will be available. This value is determined by the
input frequency of the device. Address bits A14–A12 determine the setting (see
grammable Wait State Settings,” on page
The wait state command sequence instructs the device to set a particular number of clock cycles
for the initial access in burst mode. The number of wait states that should be programmed into
the device is directly related to the clock frequency.
Configuration Register
Synchronous Mode
Figure 14.1 Synchronous/Asynchronous State Diagram
Set Burst Mode
Command for
(A19 = 0)
Asynchronous Read
Synchronous Read
S29WS128J/064J
Hardware Reset
Mode Only
Mode Only
Power-up/
D a t a
65).
Configuration Register
Asynchronous Mode
Set Burst Mode
Command for
S h e e t
(A19 = 1)
S29WS-J_M0_A4 June 24, 2005
Table 14.1, “Pro-