s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 171

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

170
Notes:
1.
2.
3.
4.
5.
6.
Standby
Read
Write
No Operation
PAR
DPD
Load
Configuration
Register
When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in select mode, only DQ[7:0]
are affected. When UB# only is in the select mode, DQ[15:8] are affected.
When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are internally
isolated from any external influence.
When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os.
The device consumes active power in this mode whenever addresses are changed.
V
DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
Mode
IN
= V
CCQ
or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current.
Deep Power-
Partial Array
Standby
Refresh
Power
Active
Active
Active
Down
Idle
Aysnc/Page CellularRAM Type 2
CE#
A d v a n c e
H
H
H
L
L
L
L
Table 35.2 Bus Operations
WE#
X
H
X
X
X
L
L
OE#
X
X
X
X
X
X
L
I n f o r m a t i o n
LB#/
UB#
X
X
X
X
X
L
L
ZZ#
H
H
H
H
L
L
L
DQ[15:0]1
Data-Out
Data-In
High-Z
High-Z
High-Z
High-Z
X
CellRAM_05_A0 August 25, 2005
(note 1),(note 3),(note
(note 2),(note 5)
(note 1),(note 4)
(note 4),(note 5)
(note 6)
(note 6)
Notes
4)