s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 176

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

38.4 Deep Power-Down Operation
August 25, 2005 CellRAM_05_A0
Deep Power-Down (DPD) operation disables all refresh-related activity. This mode is used when
the system does not require the storage provided by the CellularRAM device. Any stored data be-
comes corrupted when DPD is entered. When refresh activity is re-enabled, the CellularRAM
device requires 150 µs to perform an initialization procedure before normal operations can re-
sume. READ and WRITE operations are ignored during DPD operation.
The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0). DPD is
initiated by bringing ZZ# to the LOW state for longer than 10 µs. Returning ZZ# to HIGH causes
the device to exit DPD and begin a 150-µs initialization process. During this 150−µs period, the
current consumption is higher than the specified standby levels, but considerably lower than the
active current specification.
Driving ZZ# LOW puts the device in the PAR mode if the SLEEP bit in the CR is set HIGH
(CR[4] = 1).
The device should not be put into DPD using CR software access.
A d v a n c e
Figure 38.1 Software Access PAR Functionality
Aysnc/Page CellularRAM Type 2
I n f o r m a t i o n
NO
PAR permanently
independent of
To enable P AR,
bring ZZ# LOW
Change to ZZ#
functionality .
executed?
Power -Up
ZZ# level.
enabled,
for 10μs.
Software
LOAD
YES
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