s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 104

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A22–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The
102
Addresses
Configuration Register must be set to the Synchronous Read Mode.
AVD#
CLK
WE#
Data
OE#
CE#
V
CC
t
t
t
ACS
CAS
CSW
555h
t
VCS
Figure 22.13 Synchronous Program Operation Timings: WE# Latched Addresses
t
AVSW
t
AH
t
WP
t
AVCH
Program Command Sequence (last two cycles)
t
AVDP
t
WC
A0h
t
WPH
PA
S29WS128J/064J
D a t a
t
t
DH
DS
PD
t
S h e e t
CH
VA
t
WHWH1
Progress
Read Status Data
In
S29WS-J_M0_A4 June 24, 2005
VA
Complete