s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 73

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

14.8
14.9
June 24, 2005 S29WS-J_M0_A4
Chip Erase Command Sequence
Sector Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these oper-
ations.
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section on page 80 for information
on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
The host system may also initiate the chip erase command sequence while the device is in the
unlock bypass mode. The command sequence is two cycles cycles in length instead of six cycles.
See
sequences.
Figure 14.3, “Erase Operation,” on page 73
to the Erase/Program Operations table in the AC Characteristics section for parameters and timing
diagrams.
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ-
ing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written,
and are then followed by the address of the sector to be erased, and the sector erase command.
Table 14.5, “Command Definitions,” on page 77
sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-out of no less than 50 µs occurs.
During the time-out period, additional sector addresses and sector erase commands may be writ-
ten. Loading the sector erase buffer may be done in any sequence, and the number of sectors
may be from one sector to all sectors. The time between these additional cycles must be less than
50 µs, otherwise erasure may begin. Any sector erase address and command following the ex-
ceeded time-out may or may not be accepted. It is recommended that processor interrupts be
disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled
after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is input
during the time-out period, the normal operation will not be guaranteed.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3:
Sector Erase Timer” section on page 85.) The time-out begins from the rising edge of the final
WE# pulse in the command sequence.
Table 14.5, “Command Definitions,” on page 77
Table 14.5, “Command Definitions,” on page 77
D a t a
S h e e t
S29WS128J/064J
illustrates the algorithm for the erase operation. Refer
shows the address and data requirements for the
for details on the unlock bypass command
shows the address and data requirements
71