s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 132

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

March 9, 2005 CellRam_03_A0
Note: All burs WRITEs are continuous.
All must be set to "0"
Reserved
BCR[19]
A[21:20]
21–20
0
1
Register
BCR[15]
A d v a n c e
Select
0
1
Select RCR
Select BCR
19
A19
BCR[13]
Must be set to "0"
0
0
0
0
1
1
1
1
Reserved
Table 29.1 Bus Configuration Register Definition
A[18:16]
18–16
Synchronous burst access mode
Asynchronous access mode (default)
BCR[10]
BCR[12] BCR[11]
Register Select
0
1
0
0
1
1
0
0
1
1
Operating
BCR[8]
Mode
Operation Mode
0
1
15
A15
Active LOW
Active HIGH (default)
0
1
0
1
0
1
0
1
Must be set to "0"
Reserved
Asserted during delay
Asserted one data cycle before delay (default)
Code 0–Reserved
Code 1–Reserved
Code 2
Code 3 (Default)
Code 4–Reserved
Code 5–Reserved
Code 6–Reserved
Code 7–Reserved
14
Latency Counter
A14
WAIT Polarity
A13
13 12 11
Counter
Latency
I n f o r m a t i o n
WAIT Configuration
A12A11 A10
CellularRAM Type 2
Polarity
WAIT
10
Must be set to "0"
Reserved
9
A9
Configuration (WC)
WAIT
8
A8
BCR[6]
0
1
Must be set to "0"
Reserved
BCR[5]
Not supported
Rising edge (default)
7
A7
0
1
BCR[3]
Configuration (CC)
0
1
Full Drive (default)
1/4 Drive
Clock Configuration
Output Impedance
Clock
BCR[2]
6
0
0
0
1
A6
Burst wraps within the burst length
Burst no wrap (default)
BCR[1] BCR[0]
0
1
1
1
Impedance
Output
Burst Wrap (Note 1)
5
A5
1
0
1
1
Must be set to "0"
Reserved
4 words
8 words
16 words
Continuous burst (default)
4
A4
Burst Length (Note 1)
Wrap (BW)*
Burst
A3
3
Length (BL)*
2
A2 A1 A0
Burst
1
0
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