s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 181

• Manufacturer Part Number: s71gs256nc0bawak0
• Description: Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
• Manufacturer: Meet Spansion Inc.

December 15, 2004 cellRAM_02_A0
CR[2]
0
0
0
0
1
1
1
1
CR[7]
0
1
CR[6] CR[5]
1
0
0
1
All must be set to "0"
Page Mode Disabled (default)
Page Mode Enabled
1
0
1
0
CR[1]
Page Mode Enable/Disable
0
0
1
1
0
0
1
1
RESERVED
+15 C
+85 C (default)
+70 C
+45 C
Maximum Case Temp.
A[21:8]
21–8
CR[0]
A d v a n c e
Table 68. 64Mb Address Patterns for PAR (CR[4] = 1)
0
1
0
1
0
1
0
1
Table 67. Configuration Register Bit Mapping
PAGE
7
A7
Three-quarters of die
Three-quarters of die
One-quarter of die
One-quarter of die
One-half of die
One-half of die
Active Section
None of die
6
TCR
A6
Full die
I n f o r m a t i o n
5
A5
CellularRAM-2A
SLEEP
CR[4]
0
1
4
A4
Must be set to "0"
RESERVED
DPD Enabled
PAR Enabled (default)
3
A3
000000h–3FFFFFh
000000h–2FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
100000h–3FFFFFh
200000h–3FFFFFh
300000h–3FFFFFh
Sleep Mode
Address Space
CR[2]
2
0
0
0
0
1
1
1
1
A2
0
CR[1]
0
0
1
1
0
0
1
1
PAR
CR[0]
1
A1
0
1
0
1
1
0
0
1
None of array
Top 1/4 array
Full array (default)
Bottom 3/4 array
Bottom 1/2 array
Bottom 1/4 array
Top 3/4 array
Top 1/2 array
PAR Refresh Coverage
4 Meg x 16
3 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
3 Meg x 16
2 Meg x 16
1 Meg x 16
0
A0
Size
Configuration
Address Bus
Register
Density
64Mb
48Mb
32Mb
16Mb
48Mb
32Mb
16Mb
0Mb
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