s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 173

• Manufacturer Part Number: s71gs256nc0bawak0
• Description: Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
• Manufacturer: Meet Spansion Inc.

CellularRAM-2A
64 Megabit
Asynchronous CellularRAM
Features
T Asynchronous and Page Mode interface
T Random Access Time: 70 ns
T Page Mode Read Access
T V
T Low Power Consumption
T Low-Power Features
General Description
December 15, 2004 cellRAM_02_A0
— Sixteen-word page size
— Interpage read access: 70 ns
— Intrapage read access: 20 ns
— 1.70 V to 1.95 V V
— 1.70 V to 2.25 V V
— Asynchronous READ < 25 mA
— Intrapage READ < 15 mA
— Standby: 100 µA
— Deep power-down < 10 µA
— Temperature Compensated Refresh (TCR)
— Partial Array Refresh (PAR)
— Deep Power-Down (DPD) Mode
CC
, V
CCQ
Voltages
CellularRAM™ products are high-speed, CMOS dynamic random access memories
that have been developed for low-power portable applications. The 64Mb device
is organized as 4 Meg x 16 bits. These devices include the industry-standard,
asynchronous memory interface found on other low-power SRAM or Pseudo
SRAM offerings.
A user-accessible configuration register (CR) has been included to define device
operation. The CR defines how the CellularRAM device performs on-chip refresh
and whether page mode read accesses are permitted. This register is automati-
cally loaded with a default setting during power-up and can be updated at any
time during normal operation.
To operate smoothly on an asynchronous memory bus, CellularRAM products
have incorporated a transparent self refresh mechanism. The hidden refresh re-
quires no additional support from the system memory controller and has no
significant impact on device read/write performance.
Special attention has been focused on current consumption during self refresh.
CellularRAM products include three system-accessible mechanisms used to min-
imize refresh current. Temperature compensated refresh (TCR) is used to adjust
the refresh rate according to the case temperature. The refresh rate can be de-
creased at lower temperatures to minimize current consumption during standby.
Setting the sleep enable pin ZZ# to LOW enables one of two low-power modes:
partial array refresh (PAR); or deep power-down (DPD). PAR limits refresh to only
that part of the DRAM array that contains essential data. DPD halts refresh oper-
CC
CCQ
A d v a n c e
I n f o r m a t i o n
CellularRAM-2A
173