s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 121

• Manufacturer Part Number: s71gs256nc0bawak0
• Description: Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
• Manufacturer: Meet Spansion Inc.

Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See
Note: Non-default BCR setting: WAIT active LOW.
Note: Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is trans-
ferred on the next clock cycle.
October 4, 2004 cellRAM_00_A0
DQ[15:0]
BCR[13:11]
WAIT
WAIT
CLK
010
011
100
Latency Counter (BCR[13:11]): Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the begin-
ning of a READ or WRITE operation and the first data value transferred. Latency
codes from two (three clocks) to six (seven clocks) are allowed (see
Figure 36
CONFIGURATION CODE
3 (4 clocks)—default
2 (3 clocks)
4 (5 clocks)
LATENCY
below).
Figure 35. WAIT Configuration During Burst Operation
A d v a n c e
DQ[15:0]
WAIT
Table 21. Variable Latency Configuration Codes
CLK
D [ 0 ]
Figure 34. WAIT Configuration (BCR[8] = 1)
I n f o r m a t i o n
NORMAL
Data valid (or invalid) after one clock delay
High-Z
CellularRAM Type 2
2
3
4
LATENCY (Note)
D [ 1 ]
COLLISION
REFRESH
D [ 2 ]
6
4
8
D a t a [ 0 ]
D [ 3 ]
Legend:
MAX INPUT CLK FREQUENCY (MHz)
70ns/80 MHz
75 (13.0ns)
80 (12.5ns)
D [ 4 ]
Figure
Table 21
Don't care
35.
BCR[8] = 0
DATA VALID IN CURRENT CYCLE
BCR[8] = 1
DATA VALID IN NEXT CYCLE
and
85ns/66 MHz
44 (22.7ns)
66 (15.2ns)
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