s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 120

• Manufacturer Part Number: s71gs256nc0bawak0
• Description: Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
• Manufacturer: Meet Spansion Inc.

Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See
120
Output Impedance (BCR[5:4]): Default = Outputs Use Full Drive
Strength
The output driver strength can be altered to full, one-half, or one-quarter
strength to adjust for different data bus loading scenarios. The reduced-strength
options are intended for stacked chip (Flash + CellularRAM) environments when
there is a dedicated memory bus. The reduced-drive-strength option minimizes
the noise generated on the data bus during READ operations. Normal output drive
strength should be selected when using a discrete CellularRAM device in a more
heavily loaded data bus environment. Outputs are configured at full drive
strength during testing.
WAIT Configuration (BCR[8]): Default = WAIT Transitions One
Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAI T transitions between
the asserted and the de-asserted state with respect to valid data presented on
the data bus. The memory controller will use the WAIT signal to coordinate data
transfer during synchronous READ and WRITE operations. When BCR[ 8] = 0,
data will be valid or invalid on the clock edge immediately after WAIT transitions
to the de-asserted or asserted state, respectively
When A8 = 1, the WAIT signal transitions one clock period prior to the data bus
going valid or invalid
WAIT Polarity (BCR[10]): Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH
or LOW . This bit will determine whether the WAIT signal requires a pull-up or pull-
down resistor to maintain the de-asserted state.
BCR[5]
DQ[15:0]
0
0
1
1
WAIT
CLK
Figure 33. WAIT Configuration (BCR[8] = 0)
(Figure
High-Z
Table 20. Output Impedance
Data immediately valid (or invalid)
A d v a n c e
34).
CellularRAM Type 2
BCR[4]
0
1
0
1
D a t a [ 0 ]
I n f o r m a t i o n
(Figure 33
D a t a [ 1 ]
DRIVE STRENGTH
Figure
Reserved
Full
1/ 2
1/ 4
and
35.
Figure
cellRAM_00_A0 October 4, 2004
35).