am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 95

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

8–7 PORTSEL[1:0]
6
5
4
1-962
CSR15[1:0]
PORTSEL
0 X
0 X
0 0
0 1
1 0
1 1
AMD
FCOLL
DRTY
INTL
(BCR2 [1])
ASEL
X
X
1
1
0
0
AUI drivers rest when the AUI
transmit port is idle. When TSEL
= 0, DO+ and DO– yield “zero”
differential to operate trans-
former coupled loads (Ethernet 2
and 802.3). When TSEL = 1, the
DO+ idles at a higher value with
respect to DO– , yielding a logical
HIGH state (Ethernet 1).
This bit only has meaning when
the AUI network interface is
selected.
Read/write accessible only when
STOP bit is set. Cleared by
H_RESET or S_RESET.
Port Select bits allow for software
controlled selection of the net-
work medium.
PORTSEL settings of AUI and
10BASE-T are ignored when the
ASEL bit of BCR2 (bit 1) has
been set to ONE.
The network port configurations
are as follows:
Read/write accessible only when
STOP bit is set. Cleared by
H_RESET or S_RESET and is
unaffected by STOP.
Internal Loopback. See the de-
scription of LOOP, CSR15[2].
Read/write accessible only when
STOP bit is set.
Disable Retry. When DRTY = “1”,
PCnet-PCI controller will attempt
only one transmission. If DRTY =
“0”, PCnet-PCI controller will at-
tempt 16 transmissions before
signaling a retry error.
Read/write accessible only when
STOP bit is set.
Force Collision. This bit allows
the collision logic to be tested.
PCnet-PCI controller must be in
internal loopback for FCOLL to
be valid. If FCOLL = “1”, a colli-
sion will be forced during loop-
back transmission attempts; a
(of 10BASE-T)
Status
Pass
Link
Fail
X
X
X
X
10BASE-T
10BASE-T
Reserved
Reserved
Network
P R E L I M I N A R Y
Port
AUI
AUI
Am79C970
3
2
1
LOOP
0
1
1
1
DXMTFCS
LOOP
DTX
INTL
X
0
1
1
MENDECL
Retry Error will ultimately result.
If FCOLL = “0”, the Force Colli-
sion logic will be disabled.
FCOLL is defined after the In-
itialization Block is read.
Read/write accessible only when
STOP bit is set.
Disable Transmit CRC (FCS).
When DXMTFCS = 0, the trans-
mitter will generate and append a
FCS to the transmitted frame.
When DXMTFCS = 1, the FCS
logic is allocated to the receiver
and no FCS is generated or sent
with
DXMTFCS is overridden when
ADD_FCS is set in TMD1.
See also the ADD_FCS bit in
TMD1. If DXMTFCS is set and
ADD_FCS is clear for a particular
frame, no FCS will be generated.
The value of ADD_FCS is valid
only when STP is set in TMD1. If
ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry.
In loopback mode, this bit deter-
mines if the transmitter appends
FCS or if the receiver checks the
FCS.
This bit was called DTCR in the
LANCE (Am7990).
Read/write accessible only when
STOP bit is set.
Loopback
PCnet-PCI controller to operate
in full duplex mode for test pur-
poses. When LOOP = “1”, loop-
back is enabled. In combination
with INTL and MENDECL, vari-
ous loopback modes are defined
as follows:
X
X
Read/write accessible only when
STOP bit is set. LOOP is cleared
by H_RESET or S_RESET and is
unaffected by STOP.
Disable
PCnet-PCI controller not access-
ing the Transmit Descriptor Ring
0
1
the
Non-loopback
External Loopback
Internal Loopback
Include MENDEC
Internal Loopback
Exclude MENDEC
Transmit
transmitted
Loopback Mode
Enable
results
frame.
allows
in