am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 120

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

0
BCR20: Software Style
Bit
31–16 RES
15–10 RES
9
8
CSRPCNET
EDI/EDO
SSIZE32
Name
EEPROM Data In / EEPROM
Data Out. Data that is written to
this bit will appear on the EEDI
output of the Microwire interface,
except when the PREAD bit is set
to ONE or the EEN bit is set to
ZERO. Data that is read from this
bit reflects the value of the EEDO
input of the Microwire interface.
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit is
set to ZERO and the EEN bit is
set to ONE.
EDI/EDO is reset to ZERO by
H_RESET and is not affected by
S_RESET or STOP.
Description
This register is an alias of the lo-
cation CSR58. Accesses to/from
this register are equivalent to ac-
cesses to CSR58.
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Written as
ZEROs and read as undefined.
CSR PCnet-ISA configuration
bit. When set, this bit indicates
that the PCnet-PCI controller
register bits of CSR4 and CSR3
will map directly to the CSR4 and
CSR3 bits of the PCnet-ISA
(Am79C960)
cleared, this bit indicates that
PCnet-PCI controller register bits
of CSR4 and CSR3 will map di-
rectly to the CSR4 and CSR3 bits
of
device.
The value of CSRPCNET is de-
termined by the PCnet-PCI con-
troller. CSRPCNET is read only
by the host.
The PCnet-PCI controller uses
the setting of the Software Style
register (BCR20 bits7-0/CSR58
bits 7-0) to determine the value
for this bit.
CSRPCNET is set by H_RESET
and is not affected by S_RESET
or STOP.
Software Size 32 bits. When set,
this bit indicates that the PCnet-
PCI
the
controller
ILACC
device.
(Am79C900)
P R E L I M I N A R Y
utilizes
When
Am79C970
Am79C900 (ILACC) software
structures. In particular, Initiali-
zation Block and Transmit and
Receive descriptor bit maps are
affected. When cleared, this bit
indicates that the PCnet-PCI
controller
(PCnet-ISA) software structures.
Note: Regardless of the setting
of SSIZE32, the Initialization
Block must always begin on a
double-word boundary.
The value of SSIZE32 is deter-
mined by the PCnet-PCI control-
ler. SSIZE32 is read only by the
host.
The PCnet-PCI controller uses
the setting of the Software Style
register (BCR20, bits 7-0/CSR58
bits 7-0) to determine the value
for this bit. SSIZE32 is cleared by
H_RESET and is not affected by
S_RESET or STOP.
If SSIZE32 is reset, then bits
IADR[31–24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32 bit address
bus during master accesses initi-
ated by the PCnet-PCI controller.
This action is required, since the
16-bit software structures speci-
fied by the SSIZE32=0 setting
will yield only 24 bits of address
for PCnet-PCI controller bus
master accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the PCnet-PCI controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the PCnet-PCI
controller for performing master
accesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address pins. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit.
utilizes
Am79C960
AMD
1-987