am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 81

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

Running Registers
The following is a list of those registers that would typi-
cally need to be periodically read and perhaps written
during the normal running operation of the PCnet-PCI
controller within a system. Each of these registers con-
tains control bits or status bits or both.
PCI Configuration Registers
The PCnet-PCI controller supports the 64-byte header
portion of the configuration space as defined by the PCI
specification revision 2.0. None of the device specific
registers in locations 64 – 255 are used. The layout of
the configuration registers in the header region is shown
in the table below. All registers required to identify the
PCnet-PCI controller and its function are implemented.
Additional registers are used to setup the configuration
of the PCnet-PCI controller in a system.
The configuration registers are accessible only by PCI
configuration cycles. They can be accessed right after
1-948
31
CSR122
BCR2
BCR18
BCR20
RAP
CSR0
CSR4
CSR112
CSR114
AMD
Base-Class
Reserved
Reserved
Receiver Packet Alignment Control
Misc. configuration
Bus Size and Burst Control Register
Software Style
Register Address Port Register
PCnet-PCI controller Status Register
Test and Features Control
Missed Frame Count
Receive Collision Count
Device ID
24 23
Status
Header Type
Sub-Class
Reserved
P R E L I M I N A R Y
Base Address
16 15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Am79C970
Programming IF
Latency Timer
the PCnet-PCI controller is powered-on, even if the read
operation of the serial EEPROM is still on-going. All
multi-byte numeric fields follow little endian byte order-
ing. The Command register is the only register cleared
by H_RESET. S_RESET as well as asserting SLEEP
have no effect on the value of the PCI configuration reg-
isters. All write accesses to Reserved locations have no
affect, reads from these locations will return a data value
of ZERO.
Vendor ID (Offset 00h)
The Vendor ID register is a 16-bit register that identifies
the manufacturer of the PCnet-PCI controller. Ad-
vanced Micro Devices, Inc.’s (AMD) Vendor ID is 1022h.
Note that this vendor ID is not the same as the Manufac-
turer ID in CSR88 and CSR89. The vendor ID is as-
signed by the PCI Special Interest Group.
The Vendor ID register is located at offset 00h in the PCI
Configuration Space. It is read only.
Device ID Register (Offset 02h)
The Device ID register is a 16-bit register that uniquely
identifies the PCnet-PCI controller within AMD’s prod-
uct line. The PCnet-PCI Device ID is 2000h. Note that
this Device ID is not the same as the Part number in
CSR88 and CSR89. The Device ID is assigned by Ad-
vanced Micro Devices, Inc.
The Device ID register is located at offset 02h in the PCI
Configuration Space. It is read only.
Interrupt Pin
Command
Vendor ID
8 7
Interrupt Line
Revision ID
Reserved
0
Offset
0Ch
1Ch
2Ch
3Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h