am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 38

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

Note that the number of transfer cycles for each FRAME
assertion will always only be controlled by LINBC, Bus
Grant and FIFO conditions. The number of transfer cy-
cles for each FRAME assertions will not be affected by
DMAPLUS or by the values in the DMA Transfer Count
register and Bus Timer register. However, these factors
can influence the number of transfers that is performed
during any given bus mastership period.
Barring a time-out by the DMA Transfer Count register
or the Bus Timer register or a bus preemption by another
mastering device, the FIFO watermark settings and the
extent of Bus Grant latency will be the major factors in
determining the number of accesses performed during
any given bus mastership period. The TRDY response
time of the memory device will also affect the number of
transfers, since the speed of the accesses will affect the
state of the FIFO. (During accesses, the FIFO may be
If DMAPLUS = 0, a maximum of 16 transfers will
be performed by default. This default value may be
changed by writing to the DMA Transfer Counter
(CSR80). Note that DMAPLUS = 0 merely sets a
maximum value. The minimum number of transfers
in the bus mastership period will be determined by
all of the following variables: the settings of the
FIFO watermarks and the conditions of the FIFOs,
the value of the DMA Transfer Counter (CSR80),
the value of the DMA Bus Timer (CSR82), and any
occurrence of preemption that takes place during
the bus mastership period.
If DMAPLUS = 1, linear bursting will continue until
the transmit FIFO is filled to its high threshold
(read transfers) or the receive FIFO is emptied to
its low threshold (write transfers), or until the DMA
Bus Timer value (CSR82) has expired. A bus
preemption event is another cause of termination
of cycles. The FIFO thresholds are programmable
(see description of CSR80), as are the DMA
Transfer Counter and Bus Timer values. The exact
number of total transfer cycles in the case of
DMAPLUS = 1 will be dependent on the latency of
the system bus to the PCnet-PCI controller’s ma-
stership request and the speed of bus operation,
but will be limited by the value in the Bus Timer
Register, the FIFO condition and by preemption
occurrences, if any.
P R E L I M I N A R Y
Am79C970
filling or emptying on the network end. For example, on a
Receive operation, a slower device will allow additional
data to accumulate inside of the FIFO. If the accesses
are slow enough, a complete DWORD may become
available before the end of the bus mastership period
and thereby increase the number of transfers in that pe-
riod.) The general rule is that the longer the Bus Grant
latency or the slower the bus transfer operations or the
slower the clock speed or the higher the transmit water-
mark or the lower the receive watermark or any combi-
nation thereof, will produce longer total burst lengths.
Linear Burst DMA Starting Address Restrictions
A PCnet-PCI controller linear burst will begin only when
the address of the current transfer meets the following
condition:
The following table illustrates all possible starting ad-
dress values for all legal LINBC values. Note that
AD[31:06] are don’t care values for all addresses. Also
note that while AD[1:0] do not physically exist within a 32
bit system (the PCnet-PCI controller always drives
AD[1:0] to ZERO during the address phase to indicate a
linear burst order), they are valid bits within the buffer
pointer field of descriptor word 0. Thus, where AD[1:0]
are listed, they refer to the lowest two bits of the descrip-
tors buffer pointer field. These bits will have an affect on
determining when a PCnet-PCI controller linear burst
operation may legally begin and they will affect the out-
put values of the byte enable pins, therefore they have
been included in the table as AD[1:0].
LINBC[2:0]
0, 3, 5, 7
AD[31:00] MOD (LINBC x 16) = 0,
1
2
4
Table 3. Linear Burst DMA Starting
Linear Burst
(number of
transfers)
Reserved
LBS =
Size
16
4
8
Address Values
Reserved
Size of
(bytes)
Burst
16
32
64
Beginning Addresses
Not Applicable
00, 10, 20, 30
Linear Burst
(AD[31:06] =
(don’t care)
AD[5:0] =
00, 20
(Hex)
00
AMD
1-905