am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 82

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

Command Register (offset 04h)
The Command register is a 16-bit register used to con-
trol the gross functionality of the PCnet-PCI controller. It
controls the PCnet-PCI controller’s ability to generate
and respond to PCI bus cycles. To logically disconnect
the PCnet-PCI device from all PCI bus cycles except
Configuration cycles, a value of ZERO should be written
to this register.
The Command register is located at offset 04h in the PCI
Configuration Space. It is read and written by the host.
15-10
9
8
7
6
SERREN
PERREN
FBTBEN
ADSTEP
RES
Reserved locations. Read as
ZERO, write operations have no
effect.
Fast Back-to-Back enable. Read
as ZERO, write operations have
no effect. The PCnet-PCI con-
troller will not generate Fast
Back-to-Back cycles.
SERR enable. Controls the as-
sertion of the SERR pin. SERR is
disabled
cleared. SERR will be asserted
on detection of an address parity
error and if both, SERREN and
PERREN (bit 6 of this register)
are set.
SERREN is cleared by H_RE-
SET and is not effected by
S_RESET
SLEEP pin.
Address/data stepping. Read as
ONE, write operations have no
effect. The PCnet-PCI controller
uses address stepping for the
first address phase of each bus
master period. FRAME will be
asserted on the second CLK fol-
lowing the assertion of GNT indi-
cating a valid address on the
AD bus.
Parity Error Response enable.
Enables the parity error re-
sponse functions. When PER-
REN is ‘0’ and the PCnet-PCI
controller detects a parity error, it
only sets the Detected Parity Er-
ror bit in the Status register.
When PERREN is ‘1’, the PCnet-
PCI controller asserts PERR on
the detection of a data parity er-
ror. It also sets the DATAPERR
bit (bit 8 in the Status register),
when the data parity error oc-
curred during a master cycle.
PERREN also enables reporting
address parity errors through the
SERR pin and the SERR bit in
the Status register.
when
or
asserting
SERREN
P R E L I M I N A R Y
the
Am79C970
is
5
4
3
2
1
0
Status Register (Offset 06h)
The Status register is a 16-bit register that contains
status information for the PCI bus related events. It is lo-
cated at offset 06h in the PCI Configuration Space.
15
VGASNOOP
SCYCEN
MEMEN
MWIEN
BMEN
PERR
IOEN
PERREN
H_RESET and is not effected by
S_RESET
SLEEP pin.
VGA palette snoop. Read as
ZERO, write operations have no
effect.
Memory Write and Invalidate Cy-
cle enable. Read as ZERO, write
operations have no effect. The
PCnet-PCI controller only gener-
ates Memory Write cycles.
Special Cycle enable. Read as
ZERO, write operations have no
effect. The PCnet-PCI controller
ignores
operations.
Bus Master enable. Setting
BMEN enables the PCnet-PCI
controller to become a bus mas-
ter on the PCI bus. The host must
set BMEN before setting the INIT
bit in CSR0 of the PCnet-PCI
controller. (Setting INIT causes
the PCnet-PCI controller to start
its first bus master operation,
which is reading in the initializa-
tion block.)
BMEN is cleared by H_RESET
and is not effected by S_RESET
or asserting the SLEEP pin.
Memory Space access enable.
Read as ZERO, write operations
have no effect. The PCnet-PCI
controller
mapped resources.
I/O Space access enable. The
PCnet-PCI controller will ignore
all I/O accesses when IOEN is
cleared. The host must set IOEN
before the first I/O access to the
device. The Base Address regis-
ter at offset 10h must be pro-
grammed
address before setting IOEN.
IOEN is cleared by H_RESET
and is not effected by S_RESET
or asserting the SLEEP pin.
Parity Error. PERR is set when
the PCnet-PCI controller detects
a parity error.
The PCnet-PCI controller sam-
ples the AD[31:00], C/BE[3:0]
all
with
has
or
is
Special
asserting
a
cleared
no
AMD
valid
memory
1-949
Cycle
the
I/O
by