am79c970 Advanced Micro Devices, am79c970 Datasheet - Page 105

• Manufacturer Part Number: am79c970
• Description: Pcnettm-pci Single-chip Ethernet Controller For Pci Local Bus
• Manufacturer: Advanced Micro Devices

7–0 DMATC[7:0]
1-972
AMD
Combinations of watermark set-
tings and LINBC (BCR18, bits
2–0) settings must obey the
following relationship:
Combinations of watermark and
LINBC settings that violate this
rule may cause unexpected
behavior.
DMA Transfer Counter. This
counter contains the maximum
allowable number of transfers to
system memory that the Bus In-
terface Unit will perform during a
single bus mastership period.
The DMA Transfer Counter is not
used to limit the number of trans-
fers during Descriptor transfers.
A value of ZERO will be inter-
preted as one transfer. During
H_RESET or S_RESET a value
of 16 is loaded in the DMA Trans-
fer
DMATC is unaffected by the as-
sertion of the STOP bit. If the
DMAPLUS bit in CSR4 is set the
DMA Transfer Counter is dis-
abled.
When the DMA Transfer Counter
times out in the middle of a linear
burst, the linear burst will con-
tinue until a legal starting ad-
dress is reached, and then the
PCnet-PCI controller will relin-
quish the bus.
Therefore, if linear bursting is en-
abled, and the user wishes the
PCnet-PCI controller to limit bus
activity to desired_max transfers,
then the DMA Transfer Counter
should be programmed to a value
of:
DMA
Transfer
Counter = (desired_max DIV
where DIV is the operation that
yields the INTEGER portion of
the
Read/write accessible only when
the STOP bit is set.
watermark (in bytes)
LINBC (in bytes)
Counter.
operation.
(length of burst in
transfers)) x length
of burst in transfers
The
value
P R E L I M I N A R Y
Am79C970
of
CSR82: Bus Activity Timer
Bit
31–16 RES
15–0 DMABAT
Name
Description
Reserved locations. Written as
ZEROs and read as undefined.
Bus Activity Timer Register. If the
TIMER bit in CSR4 is set, this
register contains the maximum
allowable time that PCnet-PCI
controller will take up on the sys-
tem bus during FIFO data trans-
fers for a single DMA cycle. The
Bus Activity Timer Register does
not limit the number of transfers
during Descriptor transfers.
The DMABAT value is inter-
preted as an unsigned number
with a resolution of 0.1 s. For in-
stance, a value of 51 s would be
programmed with a value of 510.
If the TIMER bit in CSR4 is set,
DMABAT is enabled and must be
initialized by the user. The
DMABAT register is undefined
until written.
If the user has NOT enabled the
Linear Burst function and wishes
the PCnet-PCI controller to limit
bus activity to MAX_TIME micro-
seconds, then the Burst Timer
should be programmed to a value
of:
where w = wait states
If the user has enabled the Linear
Burst function and wishes the
PCnet-PCI controller to limit bus
activity to MAX_TIME microsec-
onds, then the Burst Timer
should be programmed to a value
of:
where w = wait states and lbs =
linear burst size in number of
transfers per sequence
This is because the PCnet-PCI
controller may use as much as
one linear burst size plus three
transfers in order to complete the
MAX_TIME– ((11 + 4w) x
(CLK period))
MAX_TIME– (((3+lbs) x w +
10 + lbs) x (CLK period))