zl50023 Zarlink Semiconductor, zl50023 Datasheet - Page 32

• Manufacturer Part Number: zl50023
• Description: Enhanced 4 K Channel Tdm Switch With Rate Conversion
• Manufacturer: Zarlink Semiconductor

the MODE_4M Input Control pins and the OPM bit in the Control Register (Table 13, “Control Register (CR) Bits” on
page 39) indicated in the table.
11.1
When the device is in Divided Clock mode, STio0 - 31 are driven by CKi. In this mode, the output streams and
clocks have the same amount of jitter as the input clock (CKi), but the input and output data rate cannot exceed the
input data rate defined by CKi. For example, if CKi is 4.096 MHz, the input and output data rate cannot be higher
than 2.048 Mbps, and the generated output clock rates cannot exceed 4.096 MHz.
11.2
When the device is in Multiplied Clock mode, device hardware is used to multiply CKi internally. STio0 - are driven
by this internally generated clock. In this mode, the output clocks and data can run at any of the specified rates, but
they may have different jitter characteristics from the input clock (CKi). The input data rates are still limited by the
CKi rate (as per Table 1), as input data are always sampled directly by CKi.
11.3
The device can generate a limited number of clock and frame pulse output signals. All signals are synchronous to
each other and are locked to the input CKi and FPi. The device can provide outputs with the following frequencies,
with the exception that when in Divided Clock mode, the output clock rate cannot exceed the input CKi rate.
Legend:
X - Don’t care or not applicable.
Reference Lock - Refers to what signal the output pins are locked to:
Cki = Bypass. Cki is passed directly through to CKo0-3.
Cki MULT = Cki is passed through clock multiplier to CKo0-3.
Clock Source - Refers to which clock samples STi and which clock outputs STo; STi applies when STi or STio is input; STo applies when STio is output.
Multiplied
Divided
Major
Clock
Clock
Operating Mode
Multiplied Clock Mode Operation
Output Clock Frequencies
Divided Clock Mode Operation
Device
8/16 M
8/16 M
Minor
CKo0
CKo1
CKo2
CKo3
FPo0
FPo1
FPo2
FPo3
4 M
4 M
MODE_4M [1:0]
Control
00
00
11
11
Input Pins
4.096 MHz
8.192 MHz
16.384 MHz
4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
8 kHz (244 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (61 ns wide pulse)
8 kHz (244 ns, 122 ns, 61 ns or 30 ns wide pulse)
Table 8 - Generated Output Frequencies
Table 7 - ZL50023 Operating Modes
Signal
8/16 M
8/16 M
CKi
4 M
4 M
Zarlink Semiconductor Inc.
CR Register
ZL50023
OPM
Bit
0
1
32
Reference Lock
CKi MULT
CKo0-3
CKi
Output Clock Pins
Enabled
CKo0-3
Yes
CKi
STi
Clock Source
Data Sheet
Data Pins
(CKi MULT)
CKo0-3
CKo0-3
(CKi)
STo