zl50023 Zarlink Semiconductor, zl50023 Datasheet - Page 20

• Manufacturer Part Number: zl50023
• Description: Enhanced 4 K Channel Tdm Switch With Rate Conversion
• Manufacturer: Zarlink Semiconductor

5.0
The ZL50023 is capable of operating using either the ST-BUS or GCI-Bus standards. The output timing that the
device generates is defined by the bus standard. In the ST-BUS standard, the output frame boundary is defined by
the falling edge of CKo while FPo is low. In the GCI-Bus standard, the frame boundary is defined by the rising edge
of CKo while FPo goes high. The data rates define the number of channels that are available in a 125 µs frame
pulse period.
By default, the ZL50023 is configured for ST-BUS input and output timing. To set the input timing to conform to the
GCI-Bus standard, FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set. To set output timing
to conform to the GCI-Bus standard, FPO[n]P and FPO[n]POS must be set in the Output Clock and Frame Pulse
Selection Register (OCFSR). The CKO[n]P bits in the Output Clock and Frame Pulse Selection Register control the
polarity (positive-going or negative-going) of the output clocks.
6.0
The ZL50023 generates frame pulse and clock timing. There are four output frame pulse pins (FPo0 - 3) and four
output clock pins (CKo0 - 3). All output frame pulses are 8 kHz output signals. By default, the output frame
boundary is defined by the falling edge of the CKo0, while FPo0 is low. At the output frame boundary, the CKo1,
CKo2 and CKo3 output clocks will by default have a falling edge, while FPo1, FPo2 and FPo3 will be low. The
duration of the frame pulse low cycle and the frequency of the corresponding output clock are shown in Table 3 on
page 21. Every frame pulse and clock output can be tristated by programming the enable bits in the Internal Mode
Selection (IMS) register.
ST-BUS and GCI-Bus Timing
Output Timing Generation
STi
(16.384 Mbps)
FPi (61 ns)
FPINP = 0
FPINPOS = 0
FPi (61 ns)
FPINP = 1
FPINPOS = 0
FPi (61 ns)
FPINP = 0
FPINPOS = 1
FPi (61 ns)
FPINP = 1
FPINPOS = 1
CKi
(16.384 MHz)
CKINP = 0
CKi
(16.384 MHz)
CKINP = 1
STi
(8.192 Mbps)
3
Figure 6 - Input Timing when CKIN1 - 0 = “00” in the CR
1 0
2
1
0
7
7
6
5
6 5 4 3 2 1
4
Channel 0
Channel 0
3
2
1
0
7
Zarlink Semiconductor Inc.
6
5
4
ZL50023
3
2
20
3
5 4
2
Channel N = 255
1
Channel N = 127
0
7
3 2 1 0
6
5
4
3
2
1
0
7
7
6
5
6 5
4
3
2
Data Sheet