zl50023 Zarlink Semiconductor, zl50023 Datasheet - Page 15

• Manufacturer Part Number: zl50023
• Description: Enhanced 4 K Channel Tdm Switch With Rate Conversion
• Manufacturer: Zarlink Semiconductor

PBGA Pin
H13, H15,
K13, K15,
J14, H12,
G12, G13
K14, J11,
J15, H11,
J12, J13,
Number
M13
N12
R11
N11
R12
G2
LQFP Pin
Number
82, 84,
86, 87,
88, 89,
90, 91,
92, 93,
94, 96,
98, 99
211
44
40
39
42
41
MOT_INTEL
DTA_RDY
Pin Name
R/W_WR
DS_RD
RESET
A0 - 13
CS
Zarlink Semiconductor Inc.
Data Transfer Acknowledgment_Ready (5 V-Tolerant
Three-state Output)
This active low output indicates that a data bus transfer is
complete for the Motorola interface. For the Intel interface, it
indicates a transfer is completed when this pin goes from low to
high. An external pull-up resistor MUST hold this pin at HIGH level
for the Motorola mode. An external pull-down resistor MUST hold
this pin at LOW level for the Intel mode.
Chip Select (5 V-Tolerant Input)
Active low input used by the Motorola or Intel microprocessor to
enable the microprocessor port access.
Read/Write_Write (5 V-Tolerant Input)
This input controls the direction of the data bus lines (D0 - 15)
during a microprocessor access. For the Motorola interface, this
pin is set high and low for the read and write access respectively.
For the Intel interface, a write access is indicated when this pin
goes low.
Data Strobe_Read (5 V-Tolerant Input)
This active low input works in conjunction with CS to enable the
microprocessor port read and write operations for the Motorola
interface. A read access is indicated when it goes low for the Intel
interface.
Address 0 to 13 (5 V-Tolerant Inputs)
These pins form the 14-bit address bus to the internal memories
and registers.
Motorola_Intel (5 V-Tolerant Input with Internal Pull-up)
This pin selects the Motorola or Intel microprocessor interface to
be connected to the device. When this pin is unconnected or
connected to high, Motorola interface is assumed. When this pin is
connected to ground, Intel interface should be used.
Device Reset (5 V-Tolerant Input with Internal Pull-up)
This input (active LOW) puts the device in its reset state that
disables the STio0 - 31 drivers and drives the STOHZ0 - 15
outputs to high. It also preloads registers with default values and
clears all internal counters. To ensure proper reset action, the reset
pin must be low for longer than 1µs. Upon releasing the reset
signal to the device, the first microprocessor access cannot take
place for at least 600 µs due to the time required to stabilize the
device from the power-down state. Refer to Section 13.2 on
page 33 for details.
ZL50023
15
Description
Data Sheet