zl50023 Zarlink Semiconductor, zl50023 Datasheet - Page 16

no-image

zl50023

Manufacturer Part Number
zl50023
Description
Enhanced 4 K Channel Tdm Switch With Rate Conversion
Manufacturer
Zarlink Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
zl50023GAC
Manufacturer:
ATMEL
Quantity:
1 063
Part Number:
zl50023QCC
Manufacturer:
ZARLINK
Quantity:
7
Part Number:
zl50023QCG1
Manufacturer:
ZARLINK
Quantity:
7
ZL50023
Data Sheet
3.0
Device Overview
The device has thirty-two ST-BUS/GCI-Bus inputs (STi0 - 31) and thirty-two ST-BUS/GCI-Bus outputs (STio0 - 31).
STio0 - 31 can also be configured as bi-directional pins, in which case STi0 - 31 will be ignored. It is a non-blocking
digital switch with 4096 64 kbps channels and is capable of performing rate conversion between ST-BUS/GCI-Bus
inputs and ST-BUS/GCI-Bus outputs. The ST-BUS/GCI-Bus inputs accept serial input data streams with data rates
of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps on a per-stream basis. The ST-BUS/GCI-Bus outputs
deliver serial data streams with data rates of 2.048 Mbps, 4.096 Mbps and, 8.192 Mbps and 16.384 Mbps on a
per-stream basis. The device also provides sixteen high impedance control outputs (STOHZ0 - 15) to support the
use of external ST-BUS/GCI-Bus tristate drivers for the first sixteen ST-BUS/GCI-Bus outputs (STio0 -15).
By using Zarlink’s message mode capability, microprocessor data stored in the connection memory can be
broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status
information for external circuits or other ST-BUS/GCI-Bus devices.
The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define
the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The
output data streams will be driven by and have their timing defined by FPi and CKi in Divided Clock mode (CLKM
bit 11 Table 13, Control Register (CR) Bits. In Multiplied Clock mode, the output data streams will be driven by an
internally generated clock, which is multiplied from CKi internally. In Multiplied Clock mode, the output data streams
will be driven by an internally generated clock, which is multiplied from CKi internally. Refer to Application Note
ZLAN-120 for further explanation of the different modes of operation.
16
Zarlink Semiconductor Inc.

Related parts for zl50023