pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 32

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pt7a6527

Manufacturer Part Number
pt7a6527
Description
Hdlc Controller
Manufacturer
Pericom Technology Inc
Datasheet

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Interface Timing
Characteristics of Interface Timing
Figure 26 uP Read Cycle
Figure 27 uP Write Cycle
PT0080(02/09)
Sym
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ALS
DSD
t
WW
DW
WD
AA
AL
LA
AS
AH
AD
RR
RD
DF
WI
RI
Microprocessor Interface Timing in Intel Bus Mode
ALE pulse width
Address setup time to ALE
Address hold time from ALE
Address latch setup time to WR, RD
Address setup time
Address hold time
ALE guard time
RD Delay after WR setup
RD pulse width
Data output delay from RD
Data float from RD
RD control interval
WR pulse width
Data setup time to WR x CS
Data hold time from WR x CS
WR control interval
WR X CS
RD X CS
AD0-AD7
AD0-AD7
Description
High Impedance
t
RD
t
WW
t
RR
t
DW
Data
Data
32
Test Conditions
t
t
DF
WD
Vcc=5.0V
Vcc=3.3V
t
WI
t
RI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High Impedance
Min
120
50
20
35
35
10
25
15
75
60
30
10
70
0
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HDLC controller
Max
Data Sheet
60
70
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PT7A6527
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ver:4

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