pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 15

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Figure 13 Receive FIFO in the Case of Short Frame
•
2 x 32 bytes of intermediate storage are provided per HDLC
controller in the transmit direction. After ups to 32 bytes have
been written to the FIFO, transmission is started by a software
command (XHF). If the previous transmission is still
underway when a new transmission command is issued,
microcontroller access to the FIFO will be blocked until the
first transmission is completed (figure 14). This means that at
most one complete frame may be written to the FIFO before a
transmission is initiated. If a transmission request does not
include a frame end indicator (XME), the HDLC controller
will request the next data block via an interrupt if the FIFO
contains no more than 32 bytes. This procedure will be
repeated until the microcontroller indicates that the frame is to
be closed.
In the case when this indication is not given and there is no
more data ready for transmission, the frame is terminated with
an abort sequence and the microcontroller is notified via a
Figure 14 Transmit FIFO
PT0080(02/09)
Transmission of Frames
Inacces-
sible
to µ P
a) Prior to Transmission
Acces-
sible
to µ P
Command for Frame n+1
Frame n+1
Frame n
32 Bytes
Inaccessible
to µP
32 Bytes
Accessible
to µP
Trans-
mission
a) Prior to µP
Acknowledgement
Inacces-
sible
to µ P
Last Part of
Frame i + n
Inacces-
sible
to µ P
Frame i + 1
b) After Transmission
Frame i
Command for Frame n+1
Frame n+1
Frame n
15
0 < n < 16
transmit data underrun (XDU) interrupt. The frame may also
be aborted per software command. The completed
transmission of an HDLC frame is reported by an XPR
(Transmit Pool Ready) interrupt status.
Collision Control and Switching Function
The PT7A6527 possesses flexible collision control
capabilities that are totally transparent to the microcontroller.
The collision control modes enable use of the circuit in
statistical multiplexing applications or in centralized or de-
centralized packet switches. Each of the four HDLC
controllers is individually programmed in one of four modes
by its own register bits CMS1-0 (Collision Mode Select).
Table 4 lists the four collision modes that can be selected,
along with the auxiliary I/O lines used in each case. The
outputs TXD1 and TXD2 can be selected to be of the open-
drain or of the push-pull type.
b) After µP
Trans-
mission
Acknowledgement
Frame i + 2
Frame i + n
Frame i + 1
Acces-
sible
to µ P
c) After Interrupt
Inacces-
sible
to µ P
"Transmit Pool Ready"
Frame n+1
HDLC controller
Data Sheet
PT7A6527
Trans-
mission
Ver:4