pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 14

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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the frame, when ready, is made available to the
microcontroller (figure 12).
When a whole frame shorter than 32 bytes, or the final part of
a frame longer than that becomes available, the condition is
indicated by an RME (Receive Message End) interrupt status,
instead of RPF.
In the case of frames at least 64 bytes long, the
microcontroller will repeatedly be prompted by an interrupt lo
read out the FIFO in blocks of 32 bytes (except possibly the
final block). Again, after reading a block, the microcontroller
acknowledges the data by a software command and thus
releases the FIFO. If this is not done before an additional 32-
data bytes are received, the next data byte will lead to a data
overflow condition.
In the case of several shorter frames up to seventeen may be
stored inside the HDLC controller. After an interrupt (RME),
one frame is available in the FIFO for the microcontroller to
read. Up to sixteen other frames may be stored in the
meanwhile in the upper half of the FIFO (figure 13). When
the microcontroller releases the current data block from the
Table 3 Address Comparing Logic
Figure 12 Receive FIFO in the Case of a Frame No Longer than 64 Bytes
PT0080(02/09)
SCM
0
1
SCG
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
SCS
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
32 Bytes
Inaccessible
to µP
SGP
32 Bytes
Accessible
to µP
a) Prior to µ P
Acknowledgement
Accept all frames
Reject frames with
Reject all frames
Accept frames with
Block B
Block
B + 1
Effect
14
FIFO by software command, the next frame becomes
available and the corresponding space is freed in the upper
half for (a) subsequent frame(s) (figure 13).
The interrupts accumulating in the process are incorporated
into a queue and transferred one by one to the microcontroller
as well as additional information about the frame. In particular,
the frame length is stored in a register. Information such as
frame aborted yes/no and CRC error yes/no and data overflow
yes/no, is included in an extra byte stored in the FIFO after the
last byte of the corresponding frame.
Every interrupt has to be acknowledged by the microcontroller.
A full FIFO at the beginning of a frame will lead to a frame
overflow condition.
If the microcontroller does not wish to preserve an incoming
frame, the possibility exists to ignore it. When the
corresponding command (RMD) is issued, the part of the
frame stored is deleted and the rest of the entire frame will be
ignored.
SAPS (0D )
SAPS (0D ) and SAPP (16D )
SAPG (63D )
SAPG (63D ) and SAPP (16D )
SAPG (63D ) and SAPS (0D )
SAPG (63D ), SAPS (0D ) and SAPP (16D )
SAPP (16D )
SAPS (0D )
SAPS (0D ) and SAPP (16D )
SAPG (63D )
SAPG (63D ) and SAPP (16D )
SAPG (63D ) and SAPS (0D )
SAPG (63D ), SAPS (0D ) and SAPP (16D )
SAPP (16D )
b) After µP
Acknowledgement
Block
B + 1
Free
HDLC controller
Data Sheet
PT7A6527
Ver:4