pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 23

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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All bytes between the opening flag and the CRC field are
stored in the RFIFO.
When the frame (excluding the CRC field) is not longer than
31 bytes, the whole frame is transferred in one block. The
reception of the frame is reported via the Receive Message
End (RME) interrupt. The length of the frame can be read out
from an 8-bit register (RFBC). A status byte is appended to
the data in the RFIFO after an RME interrupt. It includes
information about the frame, such as frame aborted yes/no or
CRC valid yes/no. The frame and the status byte remain stored
until the microcontroller issues an acknowledgment (Receive
Message Complete: RMC).
A frame longer than 31 bytes is transferred to the
microcontroller in blocks of 32 bytes plus one remainder
block of length 0 to 31 bytes plus status byte. The reception of
a 32-byte block is reported by a Receive Pool Full (RPF)
interrupt and the data in RFIFO remains valid until this
Figure 21 Reception of an HDLC Frame
Transmit Frame Processing
After checking the XFIFO status by polling the Transmit
FIFO Write Enable (XFW) bit or after a Transmit Pool Ready
(XPR) interrupt, up to 32 bytes may be entered by the
microcontroller in the XFIFO. Transmission of an HDLC
frame is started when the Transmit HDLC Frame (XHF)
command is issued. The HDLC controller will request another
data block by an XPR interrupt if there are no more than 32
bytes in the XFIFO and the frame close command bit
(Transmit Message End XME) has not been set. When XME
is set, all remaining bytes in the XFIFO are transmitted, the
CRC field and the closing flag of the HDLC frame are
appended and the controller generates a new XPR interrupt
(figure 22).
PT0080(02/09)
t
PT7A6527
Receiver
HDLC
Data Transfer
Data and Status Information (Status Byte, RFBC) Transfer
(Reception of 32 Bytes)
(Reception of Remainder)
(Reception of 32 Bytes)
23
RMC
RMC
RMC
RMC
RME
RPF
RPF
RPF
interrupt is acknowledged (RMC). This process is repeated
until the reception of the remainder block reported by RME
(figure 21). Bits 0-4 of the RFBC register represent the
number of bytes stored in the RFIFO, including the status byte.
Bits 7-5 indicate the total number of 32-byte blocks which
were stored until the reception of the remainder block. Bits 7-
5 do not overflow when the counter status 7 has been reached
and indicate in this case a message length greater than 223
bytes.
The contents of the RFBC register are valid only after the
occurrence of the RME interrupt, and remain valid until the
microprocessor issues an acknowledgment (RMC). All receive
interrupts accumulated in the meantime are stored (along with
the status bytes and respective frame lengths) inside the
controller and transferred one by one to the microcontroller
after each RMC acknowledgment. If a frame could not be
stored due to a full FIFO, the microcontroller is informed of
this via the Receive Frame Overflow interrupt (RFO).
The microcontroller does not necessarily have to transfer a
frame in blocks of 32 bytes. As a matter of fact, the sub-
blocks issued by the microcontroller and separated by an XHF
command, can be between 1 and 32 bytes long.
If the XFIFO runs out of data and the XME command bit has
not been set, the frame will be terminated with an abort
sequence (seven 1s) followed by inter-frame time fill, and the
microcontroller will be advised by a Transmit Data Underrun
(XDU) interrupt. An HDLC frame may also be aborted by
setting the Transmit Reset (XRES) command bit.
Table 10 gives summary of possible interrupts from the
HDLC controller and the appropriate reaction to these
interrupts. Table 11 lists the most important commands that
are issued by a microcontroller by setting one or several bits in
the Command Register (CMDR).
System
uP
HDLC controller
Data Sheet
PT7A6527
Ver:4