pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet
pt7a6527
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pt7a6527 Summary of contents
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... PT7A6527JE Lead free and Green 44-pin PLCC PT0080(02/09) Description The ISDN Digital Exchange Controller PT7A6527 is a serial HDLC data communication circuit with four independent channels. Its telecommunication specific features make it especially suited for use in variable data rate PCM systems. In addition, the device contains ...
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... Chip Timing Power & Ground Microprocessor Interface I/O Interface PT0080(02/09) Symbol DCL, FSC, TSC GND, VCC AD0~AD7, A0~A6, RD/DS, WR/R/W, CS, ALE, INT, RES CDR, RxD0, TxD0, TxD1, RxD1, RxD2, TxD2, TxD3, RxD3 2 Data Sheet PT7A6527 HDLC controller Function Clock Power Data or Control Serial Data Ver:4 ...
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... Time-Slot Control: Supplies a control signal for an external driver. O Transmit data: Transmit data is shifted out via these pins at standard TTL or CMOS levels. O Receive data: Serial data is received on these pins at standard TTL or CMOS levels power supply. Power No connection Data Sheet PT7A6527 HDLC controller Description Ver:4 ...
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... ISDN networks to process signaling or packet data of four ISDN subscribers. In this application, it may be used with or without PCM Interface Controller (PCM Controller). Figure 1 Use of PT7A6527 in Central Signaling / Data Packet Handlers PT0080(02/09) The PT7A6527 can be connected to the IOM interface of the PCM CONTROLLER, which is itself connected to the PCM system highway ...
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... The use of a PT7A6527 in the mixed D-channel processing architecture is illustrated in figure 3. The additional transparent data connections supported by the PT7A6527 enable a merging of p and s packets into one D channel. Possible collision situations are dealt with by the PT7A6527 which uses either the additional collision detect ...
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... Figure 3 PT7A6527 on a Line Card in a Mixed D-Channel Processing Architecture IOM Line Transceivers D Line Transceivers D PT7A6527 s Note Packets will be discarded by the receiver Time-Slot for p packets Time-Slot for s packets Coll s-p = Time-Slot containinginformation about a collisionbetween s packets and p packets Functional Description General Functions ...
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... DCL) and a frame synchronization signal (input FSC). Input data is latched on the falling edge of DCL and output data is clocked off on the rising edge of DCL. The PT7A6527 may be programmed so that the data clock rate is either equal to the data rate, or twice the data rate. ...
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... Figure 4 Two Connection Modes of PT7A6527 QuadConnection a) Table 2 HDLC Controller Channel Selection and characteristics Mode Channel MDS1 MDS0 RXD0 RXD0 RXD0 RXD0 0 1 RXD0 RXD1 RXD2 RXD3 1 0 RXD0 RXD0 RXD0 RXD0 1 1 RXD0 RXD1 RXD2 RXD3 Mode Channel Characteristics ...
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... Figure 5 Operating Modes of the PT7A6527 (Continued) b) Quad Connection TS Mode Receive Transmit Receive Transmit Receive Transmit Receive Transmit Collision Data c) Single Connection TS Mode Receive Transmit Collision Data d) Single Connection IOM Mode Receive Transmit Collision Data PT0080(02/09) Slave/Multi-Master Collision Mode Programmable Time-Slots ...
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... Figure 5 Operating Modes of the PT7A6527 (Continued) e) Single Connection TS Mode Programmable Time-Slots B C Receive Transmit f) Single Connection IOM Mode IOM Receive Transmit Quad Connection Time-Slot Mode Channel selection is performed via the Time-Slot Select Registers (TSR). For each HDLC channel, the 8-bit TSR register gives the position of a time slot with a two-bit resolution ...
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... T SC PT0080(02/09) choice whether the four HDLC controllers are assigned to IOM channels governed by the microcontroller bit VIS (Common Configuration Register). See figure 10. 1 Bit TSR Bits TSR Data Sheet PT7A6527 HDLC controller Ver:4 ...
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... CH2 CH3 CH4 CH2 CH3 CH4 M M MONITOR Byte 2 Byte 3 Byte 4 CH1 CH2 CH3 CH4 Data Sheet PT7A6527 HDLC controller High Impedance TS 3C CH5 CH6 CH7 CH0 CH5 CH6 CH7 CH0 CH5 CH6 CH7 Ver:4 ...
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... FIFO) or writing (transmit FIFO) data in one 32-byte block, the other block is filled (receive FIFO) or emptied (transmit FIFO) by the PT7A6527. Thus the length of the received or transmitted frame is not limited by the FIFO size. CRC The effect of a match is programmable as shown in table 3. In the table it is assumed that the address compare enable bit (AC) is set for the channel in question ...
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... SAPS (0D ) and SAPP (16D ) SAPG (63D ) SAPG (63D ) and SAPP (16D ) SAPG (63D ) and SAPS (0D ) SAPG (63D ), SAPS (0D ) and SAPP (16D ) a) Prior to µ After µP Acknowledgement Acknowledgement Block Block B 14 Data Sheet PT7A6527 HDLC controller Free Block Ver:4 ...
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... HDLC frame is reported by an XPR (Transmit Pool Ready) interrupt status. Collision Control and Switching Function The PT7A6527 possesses flexible collision control capabilities that are totally transparent to the microcontroller. The collision control modes enable use of the circuit in statistical multiplexing applications or in centralized or de- centralized packet switches ...
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... Quad connection Time Slot mode. However, there is only one CDR line. This should especially be noted if: - The PT7A6527 is configured in the quad connection common control mode and more than one HDLC controller is operated in the slave mode; - When the same time slot is used by more than one HDLC controller in the slave mode ...
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... Programmable Time-Slots (TSR) IOM Mode Fixed Time-Slots TXD0 RXD0 PT0080(02/09) Opening Flag Time Interval for Transmission Controller A Collision Control HDLC Controller Controller B Programmable Time-Slots (TSR) TXD1 Data OUT CDR Data IN Controller C TXD2 Collision OUT Controller D 17 Data Sheet PT7A6527 HDLC controller Ver:4 ...
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... Eight 1's Opening Seven 1's Closing Flag Flag Frame from CDR Abort Opening Sequence Flag Seven 1's Frame from CDR 18 Data Sheet PT7A6527 HDLC controller Eight Bits Closing Frame Flag Frame from HDLC Controller Eight Bits Closing Frame Flag Frame from HDLC Controller Ver:4 ...
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... CDR TXD1 Test Functions A test loop is provided in each of the four HDLC controllers of the PT7A6527. When the test loop is activated, the input and the output of the HDLC channel are connected together. The test loop control is independent for each HDLC channel (bit TLP). ...
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... Operational Description Microprocessor Interface Operation The PT7A6527 microcontroller interface can be selected to be either of the - Motorola type with control signals CS, R/W, DS; address bus A0 … 6; data bus AD0 - 7 - Intel non-multiplexed bus type with control signals CS, WR, RD; Address bus A0 … 6; data bus AD0 - the Intel multiplexed address/data bus type with control signals CS, WR, RD, ALE ...
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... RFBC 00 TSR 00 Initialization The purpose of the initialization is to set the PT7A6527 into a state where it is able to correctly transfer HDLC frames and to manage collisions according to the requirements of the application. The initialization process is divided into two phases. First, the common settings are determined via the registers CCR and VISM ...
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... ISTA (and VISR) only when the mask bits in ISM (and VISM) have been reset. Processing After being initialized via the configuration/mode registers listed in table 8 and table 9 the PT7A6527 is operational. The control of the data transfer is performed by commands from the microcontroller written in the Command Register (CMDR). Events pertaining to the data transfer are reported via the Interrupt Status Register (ISTA) pointed to by the Vectored Interrupt Status Register (VISR) ...
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... Table 10 gives summary of possible interrupts from the HDLC controller and the appropriate reaction to these interrupts. Table 11 lists the most important commands that are issued by a microcontroller by setting one or several bits in the Command Register (CMDR). 23 Data Sheet PT7A6527 HDLC controller uP System Ver:4 ...
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... Transmit a HDLC Frame and close it with CRC and flag Same as preceding, but used in master mode to enforce a transmission even in the case of a collision. Reset Transmitter. Clears the XFIFO; any frame currently being transmitted is aborted. 24 Data Sheet PT7A6527 HDLC controller uP System Meaning Ver:4 ...
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... Registers The following symbols are used x... do not care n... not used. It has to be set to logical “0” in write accesses but may be switched by the PT7A6527 to either logical level in read accesses. Register Address Layout The register set consists of: - one configuration register common to all four channels CCR) ...
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... Figure 24 PT7A6527 Register Map for demultiplexed Address Bus Table 13 Address Map of HDLC Channel Register (demultiplexed address bus) Address Note: The address values in the multiplexed A/D bus and non-multiplexed address bus cases are related to each other as follows. Let AD0...7 be the multiplexed address bits and let A0...6 be the non-multiplexed address bits. ...
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... RFBC accesses is the old data loaded in that part of the RFIFO previous to the current data. For more than 32 accesses, the RFIFO will be read cyclically (modulo 32). This will not disturb the next received frame. 27 Data Sheet PT7A6527 HDLC controller Bit 0 IC1 IC0 Bit 0 ...
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... Version Number of chip: VN3 VN2 VN1 VN0 = 0010 D1 VN1 D0 VN0 PT0080(02/09) When the closing flag of a receive frame is detected, a status byte is appended to the data in the RFIFO. Description Description RFO XPR XDU n Description 28 Data Sheet PT7A6527 HDLC controller 2) a collision has occurred after at Bit Ver:4 ...
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... Not used CI3 D2 CI2 Received C/I code, will be updated in each frames. CI3 is received first. D1 CI1 D0 CI0 PT0080(02/09) Description Description Time-Slot Width 2 bits 1 bits 8 bits 7 bits Description 29 Data Sheet PT7A6527 HDLC controller Channel Data Rate (kbit/ Ver:4 ...
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... This is a stress rating only and functional )..................................-0. 7.0V CC operation of the device at these or any other condi- tions above those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 30 Data Sheet PT7A6527 HDLC controller Ver:4 ...
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... GND or Vcc Vcc=5.0V no output loads, DCLor other input to GND or Vcc Vcc=3.3V no output loads, DCLor other input to GND or Vcc 0V < V < Vcc < V < Vcc to 0V OUT - - 2.0 Test Points 0.8 31 Data Sheet PT7A6527 HDLC controller Min Typ Max Vcc + 2.2 - 0.4 Vcc + 2.0 - 0.2 -0.4 - 0.8 -0.4 - ...
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... Figure 27 uP Write Cycle AD0-AD7 PT0080(02/09) Test Conditions - - - - - - - - - Vcc=5.0V Vcc=3. High Impedance Data Data 32 Data Sheet PT7A6527 HDLC controller Min Typ Max Units 120 - - ns - ...
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... Figure 29 Non-Multiplexed Address Timing Figure 30 uP Read Cycle Figure 31 uP Write Cycle PT0080(02/09 ALS DSD RWD High Impedance Data t DSD t RWD Data 33 Data Sheet PT7A6527 HDLC controller t AH High Impedance Ver:4 ...
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... PCM frame is not equal to either 256 or 512. PT0080(02/09 Test Conditions Min Single clock rate 230 Doucle clock rate 160 - 70 Single clock rate 90 Doucle clock rate Test Conditions - - - - - - - 34 Data Sheet PT7A6527 HDLC controller t AH Typ Max Units - - - - - - - - - - Min Typ Max 110 - - ...
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... Bit of Frame t ODD t ODF 1st Bit of Frame Test Conditions FH1 FS1 FH1 t OZD t ODD t IDH t IDS 35 Data Sheet PT7A6527 HDLC controller 2nd Bit of Frame t IDS t IDH 2nd Bit of Frame t ODD t IDH t IDS 1st Bit of Frame Min Typ Max - ...
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... Data OUT Data RESET Timing Reset characteristics Sym Description t RESET HIGH RWH PT0080(02/09) Test Conditions - - - - t t IDS IDH Test Conditions Min - Data Sheet PT7A6527 HDLC controller Min Typ Max Units - - TCD Typ ...
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... Mechanical Information JE (Lead free and Green 44-pin PLCC) PT0080(02/09) 37 Data Sheet PT7A6527 HDLC controller Ver:4 ...
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... Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0080(02/09) Notes Web Site: www.pti.com.cn, www.pti-ic.com Fax: (86)-21-6485 2181 Fax: (852)- 2243 3667 Fax: (1)-408-435 1100 38 Data Sheet PT7A6527 HDLC controller Ver:4 ...