pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 16

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Table 4 Collision Modes of the PT7A6527
•
The HDLC controller transmits frames without collision
detection on the transmit line (time channel).
•
The input CDR (Collision Data Receive) is used to control
transmission of frames. This input is common to all HDLC
controllers that are programmed in the slave mode.
Transmission is inhibited by a low on the CDR input. If CDR
becomes low during the transmission of a frame, the frame is
aborted by the HDLC controller, and the data output is set to
high impedance. Refer to figure 15.
The state of CDR is evaluated by the HDLC controller only in
the time channel used for transmission by that controller.
(Figure 12 is simplified in that the grouping of bits into time
slots on TXD0 ... TXD3 and CDR is not depicted, i. e. bits
outside the transmit time channel are not shown.)
When CDR is switched high, inter-frame time fill is marked in
the transmit time channel if no transmission request is pending,
otherwise transmission starts at the first available instant.
Transmission of a previously aborted frame is automatically
re-started by the HDLC controller if the beginning of the
frame is still available in the transmit FIFO. Otherwise an
interrupt (XDU) to the microcontroller indicates that the
transmission has failed.
The slave mode is applicable in three basic operation modes
including Quad connection Common mode, Single connection
Time Slot mode and Single connection IOM mode. And in
Single connection IOM mode the TSR registers must be set to
0CH, 1CH, 2CH and 3CH for four individual channel. The
slave mode is not applicable in Quad connection Time Slot
mode. However, there is only one CDR line. This should
especially be noted if:
- The PT7A6527 is configured in the quad connection
- When the same time slot is used by more than one HDLC
In both cases more than one controller is evaluating the CDR
line during the same time interval, and when CDR goes low
they all stop transmitting.
•
In the multi-master mode the controllers perform a bus access
procedure and collision detection in their assigned time
channel(s). As a result, any number of devices can be assigned
to one physical channel, where they perform statistical
multiplexing.
PT0080(02/09)
CMS1
common control mode and more than one HDLC
controller is operated in the slave mode;
Unconditional Transmission Mode
Slave Mode
Multi-Master Mode
controller in the slave mode.
0
0
1
1
CMS0
0
1
0
1
Unconditional transmission
Slave mode
Multi-master mode
Master mode
Description
Data IN
CDR
16
Collisions are detected by automatic comparison of each
transmitted bit with the bit received via the CDR input. For
this purpose a logical and of the bits transmitted by parallel
controllers is formed and connected to the input CDR. This
may be implemented most simply by defining the output line
driver to be of the open drain type (ODS = 1). Consequently
the logical and of the outputs is formed by simply tying them
together (wired or). The result is returned to the CDR input of
all parallel circuits.
The multi-master mode is applicable in three operating modes
including Quad connection Common mode, Single connection
Time Slot mode and Single connection IOM mode. And in
Single connection IOM mode the TSR registers must be set to
0CH, 1CH, 2CH and 3CH for four individual channel. The
slave mode is not applicable in Quad connection Time Slot
mode. In the quad connection mode, those output lines
(TXD0 ... TXD3) for which this collision mode is selected
may be connected to CDR. The four HDLC controllers may
either be programmed to transmit in separate time channels or
in the same time channel. A prerequisite for the multi-master
mode is that the inter-frame time fill used is idle.
The multi-master operation is as follows (refer to figure 16).
When a mismatch between a transmitted bit and the bit on
CDR is detected, the HDLC controller stops sending further
data and its output is set to high impedance.
As soon as it detects the transmit bus to be idle” again, the
controller automatically attempts to re-transmit its frame. By
definition, the bus is assumed idle when x consecutive ones
are detected in the transmit channel. Normally x is equal to 8.
An automatic priority adjustment is implemented in the
multimaster mode. Thus, when a complete frame is
successfully transmitted, x is increased to ten, and its value is
restored to eight when a row of ten1s is detected on the bus
(CDR). Furthermore, transmission of a new frame may be
started by the HDLC controller after the tenth 1.
This multi-master, deterministic priority management ensures
an equal right of access of every HDLC controller to the
transmission medium, thereby avoiding blocking situations.
•
The master mode requires three auxiliary connections: data
input CDR, data output TXD1 and collision data out TXD2.
This mode is applicable only in single connection operation.
In the master mode, the controller performs two functions:
-
-
Master Mode
Switching of data packets between the main connection
TXD0, RXD0 and the auxiliary input and output (CDR,
TXD1)
Resolution of collisions between data from the auxiliary
connection CDR and HDLC frames from the local
microcontroller. Refer to figure 17.
Data OUT
TXD1
Auxiliary I/O
Coll. IN
CDR
CDR
HDLC controller
Data Sheet
PT7A6527
COLL. OUT
TXD2
Ver:4