pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 25

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Registers
The following symbols are used
Register Address Layout
The register set consists of:
- one configuration register common to all four channels CCR)
- a maskable vectored interrupt status register (VISR, VISM)
- a register for setting the HDLC address recognition mode or
and, for each of the four channels, a set of individual registers.
Multiplexed Address Bus
In order to support the use of a 16-bit microcontroller with
multiplexed address bus, each register can be accessed with an
even and an odd address value (figure 23).
Figure 23 PT7A6527 Register Map for a Multiplexed Bus
Table 12 Address Map of HDLC Channel Register (multiplexed address bus)
PT0080(02/09)
the four channels (ACR)
x... do not care
n... not used. It has to be set to logical “0” in write
accesses but may be switched by the PT7A6527 to
either logical level in read accesses.
Even
2C
2A
20
28
22
Address
00 to 1F
Odd
2B
29
21
25
23
34.3D
37.3E
36.3F
AF
2F
40
C0
EF
6F
80
VISR
ACR
CCR
Read
MODE
RFIFO
STAR
RFBC
Read
ISTA
CIR
25
The address map of the individual registers of each channel is
shown in table 12. In order to obtain the actual address of a
register, a base has to be added to the address given in the
table, as follows:
Non-Multiplexed Address Bus
The address layout is shown in figure 24.
The address map of the individual registers of each channel is
shown in table 13. In order to obtain he actual address of a
register, a base has to be added to the address given in the
table, as follows:
VISM
ACR
CCR
Write
base = 00 for channel A
base = 00 for channel A
Channel-A
Register Locations
Channel-B
Register Locations
Channel-C
Register Locations
Channel-D
Register Locations
40 for channel B
80 for channel C
C0 for channel D.
20 for channel B
40 for channel C
60 for channel D.
HDLC controller
CMDR
MODE
XFIFO
Write
ISM
TSR
CIX
Data Sheet
PT7A6527
Ver:4