pt7a6527 Pericom Technology Inc, pt7a6527 Datasheet - Page 27

• Manufacturer Part Number: pt7a6527
• Description: Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Address Compare Register (ACR)
-- Address: 34/3DH (1CH) Read/Write, Value after reset: 00H
Bit
Vectored Interrupt Status Register (VISR)
-- Address: 36/3FH (1EH) Read, Value after reset: xxxx0000B
or
When VISR is read, these four bits are placed on the μP data bus with an offset determined by bit VIS (register CCR). Other bit
position on the bus remain in high impedance.
Mask for Vectored Interrupt Status Register (VISM)
-- Address: 36/3FH (1 EH) Write, Value after reset: nnnn0000B
or
Individual Channel Registers
RFIFO (read), XFIFO (write)
-- Address: Base + 00 to 1 FH (Base + 00 to 0FH)
The FIFOs have an identical address range. All the 32
addresses give access to the current FIFO location.
PT0080(02/09)
D7
D6
D5
D4
D3
D2
D1
D0
Name
MIC3
MIC2
MIC1
MIC0
Name
SCM
SCG
AC3
AC2
AC1
AC0
SCS
SCP
n
n
n
n
Address Compare for channel A-D on (1) or off (0). The first byte following the opening flag of a receive frame
will be compared against reference values if ACi = 1 and the frame is accepted or rejected on the basis of the
comparison. If ACi = 0, all valid HDLC frames in that channel are stored.
SAPI Compare Mode: 1: Accept HDLC frames for which the first address byte matches selected SAPI
values. 0: Reject HDLC frames for which the first address byte matches selected SAPI values.
Compare Group 1: The first byte of a received HDLC frame is compared with ""Group SAPI"" SAPG
(63D). 0: The first byte of a received HDLC frame is not compared with SAPG
SAPI Compare Signaling 1: The first byte of a received HDLC frame is compared with ""Signaling SAPI""
SAPS (0D). 0: The first byte of a received HDLC frame is not compared with SAPS.
SAPI Compare Packet 1: The first byte of a received HDLC frame is compared with ""Packet SAPI"" SAPP
(16D). 0: The first byte of a received HDLC frame is not compared with SAPP.
It is recommended to set to 1 during write accesses.
Mask for Interrupt from Channel A-D. The mask bits are active high. A masked interrupt is not visible when
VISR is read. Instead, it remains internally stored (pending). Any pending interrupt will be generated and the
corresponding IC0-3 bit will be set when the mask bit is reset to zero.
Name
Bit 7
x
Bit 7
IC3
Bit 7
n
Bit 7
MIC3
IC3
IC2
IC1
IC0
n
x
IC2
MIC2
n
x
IC1
MIC1
n
x
IC0
MIC0
MIC3
27
IC3
Description
IC0-3 Interrupt from Channel A-D
x
n
RFIFO - The RFBC register bits 0 to 4 indicate the number of
bytes currently accessible to the microcontroller in the visible
32-byte RFIFO pool. If more bytes are read, the data read after
RFBC accesses is the old data loaded in that part of the
RFIFO previous to the current data. For more than 32 accesses,
the RFIFO will be read cyclically (modulo 32). This will not
disturb the next received frame.
Description
MIC2
IC2
Description
x
n
MIC1
IC1
x
n
Bit 0
MIC0
Bit 0
x
Bit 0
n
Bit 0
IC0
HDLC controller
Data Sheet
PT7A6527
Ver:4