tmp89fm82t TOSHIBA Semiconductor CORPORATION, tmp89fm82t Datasheet - Page 72

• Manufacturer Part Number: tmp89fm82t
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.3
Interrupt Enable Register (EIR)
RA003
Interrupt enable register (EIRL)
Interrupt enable register (EIRH)
Interrupt enable register (EIRE)
Interrupt enable register (EIRD)
Interrupt enable register (EIRC)
(0x003C)
(0x003D)
(0x003A)
(0x003B)
(0x003E)
EIRH
EIRE
EIRD
EIRC
EIRL
Note 1: Do not set the IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time.
Note 2: In the main program, before manipulating the interrupt enable flag (EF), be sure to clear the master enable flag (IMF) to
Note 3: When a read instruction is executed on EIRL, bits 3 to 1 are read as "0". Other unused bits are read as "0".
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
EF35 to
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
Bit Symbol
After reset
After reset
After reset
After reset
After reset
"0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the EF (Enable interrupt by EI
instruction)
In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if
using multiple interrupt in the interrupt service routine, manipulate the EF before setting the IMF to "1".
Function
Function
Function
Function
Function
EF4
IMF
Individual interrupt enable flag
(Specified for each bit)
Interrupt master enable flag
INTTXD0
INTTXD1
INTEDT
EF23
EF31
R/W
R/W
R/W
R/W
EF7
R
7
0
7
0
7
0
7
0
7
0
-
-
INTRXD0 /
INTRXD1
INTTCA0
INTPWM
INTSIO0
EF14
EF22
EF30
R/W
R/W
R/W
R/W
EF6
R
6
0
6
0
6
0
6
0
6
0
-
INTTCA1
INTTC01
INTPDC
INTTBT
EF13
EF21
EF29
R/W
R/W
R/W
R/W
EF5
R
5
0
5
0
5
0
5
0
5
0
-
Page 56
0:
1:
0:
1:
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
Disables the acceptance of all maskable interrupts.
Enables the acceptance of all maskable interrupts.
INTTMR3
INTTC00
INTWUC
EF12
EF20
EF28
INT4
EF4
R/W
R/W
R/W
R/W
R
4
0
4
0
4
0
4
0
4
0
-
INTSEI1
INTCLM
EF19
EF27
EF35
INT3
R/W
R/W
R/W
R/W
R
3
0
3
0
3
0
3
0
3
0
-
-
INTEMG
INTADC
INTSEI0
EF10
EF18
EF26
EF34
INT2
R/W
R/W
R/W
R/W
R
2
0
2
0
2
0
2
0
2
0
-
INTTMR2
INTVLTD
INTTC03
EF17
EF25
EF33
INT1
R/W
R/W
R/W
R/W
EF9
R
1
0
1
0
1
0
1
0
1
0
-
TMP89FM82T
master ena-
INTTMR1
INTTC02
Interrupt
ble flag
EF16
EF24
EF32
INT5
INT0
R/W
R/W
R/W
R/W
R/W
EF8
IMF
0
0
0
0
0
0
0
0
0
0