tmp89fm82t TOSHIBA Semiconductor CORPORATION, tmp89fm82t Datasheet - Page 43

• Manufacturer Part Number: tmp89fm82t
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA000
2.3.6
2.3.6.1
frequency clocks, and switches the main system clock (fm).
modes are controlled by the system control registers (SYSCR1 and SYSCR2).
Operation mode control circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-
There are three major operating modes: the single-clock mode, the dual-clock mode and the STOP mode. These
Figure 2-9 shows the operating mode transition diagram.
is 1/fcgck [s].
can be used as the I/O ports.
(1)
(2)
(3)
Only the gear clock (fcgck) is used for the operation in the single-clock mode.
The main system clock (fm) is generated from the gear clock (fcgck). Therefore, the machine cycle time
The gear clock (fcgck) is generated from the high-frequency clock (fc).
In the single-clock mode, the low-frequency clock generation circuit pins P02 (XTIN) and P03 (XTOUT)
Single-clock mode
clock (fcgck).
is released to the NORMAL1 mode.
after the interrupt processing is completed.
the IDLE1 mode activation instruction.
base timer.
become the same as the states when a reset is released. For operations of the peripheral circuits in the
IDLE0 mode, refer to the section of each peripheral circuit.
to the peripheral circuits except the time base timer.
In this mode, the CPU core and the peripheral circuits operate using the gear clock (fcgck).
The NORMAL1 mode becomes active after reset release.
In this mode, the CPU and the watchdog timer stop and the peripheral circuits operate using the gear
The IDLE1 mode is activated by setting SYSCR2<IDLE> to "1" in the NORMAL1 mode.
When the IDLE1 mode is activated, the CPU and the watchdog timer stop.
When the interrupt latch enabled by the interrupt enable register EIR becomes "1", the IDLE1 mode
When the IMF (interrupt master enable flag) is "1" (interrupts enabled), the operation returns normal
When the IMF is "0" (interrupts disabled), the operation is restarted by the instruction that follows
In this mode, the CPU and the peripheral circuits stop, except the oscillation circuits and the time
In the IDLE0 mode, the peripheral circuits stop in the states when the IDLE0 mode is activated or
The IDLE0 mode is activated by setting SYSCR2<TGHALT> to "1" in the NORMAL1 mode.
When the IDLE0 mode is activated, the CPU stops and the timing generator stops the clock supply
NORMAL1 mode
IDLE1 mode
IDLE0 mode
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TMP89FM82T