tmp89fm82t TOSHIBA Semiconductor CORPORATION, tmp89fm82t Datasheet - Page 11

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tmp89fm82t

Manufacturer Part Number
tmp89fm82t
Description
8 Bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
15. Asynchronous Serial Interface (UART)
16. Synchronous Serial Interface (SIO)
15.1 Configuration.......................................................................................................................212
15.2 Control.................................................................................................................................213
15.3 Low Power Consumption Function.....................................................................................217
15.4 Protection to Prevent UART0CR1 and UART0CR2 Registers from Being Changed .......218
15.5 Activation of STOP, IDLE0 or SLEEP0 Mode...................................................................219
15.6 Transfer Data Format...........................................................................................................220
15.7 Infrared Data Format Transfer Mode..................................................................................220
15.8 Transfer Baud Rate..............................................................................................................221
15.9 Data Sampling Method........................................................................................................225
15.10 Received Data Noise Rejection.........................................................................................227
15.11 Transmit/Receive Operation..............................................................................................228
15.12 Status Flag.........................................................................................................................229
15.13 Receiving Process..............................................................................................................236
15.14 AC Properties.....................................................................................................................238
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
14.4.8
15.5.1
15.5.2
15.8.1
15.11.1
15.11.2
15.12.1
15.12.2
15.12.3
15.12.4
15.12.5
15.12.6
15.14.1
14.4.2.1
14.4.2.2
14.4.2.3
14.4.3.1
14.4.3.2
14.4.3.3
14.4.4.1
14.4.4.2
14.4.4.3
14.4.5.1
14.4.5.2
14.4.5.3
14.4.6.1
14.4.6.2
14.4.6.3
14.4.7.1
14.4.7.2
14.4.7.3
14.4.8.1
14.4.8.2
14.4.8.3
15.8.1.1
15.8.1.2
8-bit pulse width modulation (PWM) output mode.......................................................................................................186
8-bit programmable pulse generate (PPG) output mode...............................................................................................191
16-bit timer mode...........................................................................................................................................................195
16-bit event counter mode.............................................................................................................................................199
12-bit pulse width modulation (PWM) output mode.....................................................................................................201
16-bit programmable pulse generate (PPG) output mode.............................................................................................207
Transition of register status............................................................................................................................................219
Transition of TXD pin status.........................................................................................................................................219
Transfer baud rate calculation method...........................................................................................................................222
Data transmit operation................................................................................................................................................228
Data receive operation.................................................................................................................................................228
Parity error...................................................................................................................................................................229
Framing Error..............................................................................................................................................................230
Overrun error...............................................................................................................................................................231
Receive Data Buffer Full.............................................................................................................................................234
Transmit Buffer Full....................................................................................................................................................235
IrDA properties............................................................................................................................................................238
Transmit busy flag......................................................................................................................................................235
Setting
Operation
Double buffer
Setting
Operations
Double buffer
Setting
Operation
Double buffer
Setting
Operations
Double buffer
Setting
Operations
Double buffer
Setting
Operations
Double buffer
Setting
Operations
Double buffer
Bit width adjustment using UART0CR2<RTSEL>
Calculation of set values of UART0CR2<RTSEL> and UART0DR
v

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