tmp89fm82t TOSHIBA Semiconductor CORPORATION, tmp89fm82t Datasheet - Page 65

• Manufacturer Part Number: tmp89fm82t
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA003
3. Interrupt Control Circuit
of the internal interrupt sources are non-maskable while the rest are maskable.
addresses. When a request for an interrupt is generated, its interrupt latch is set to "1", which requests the CPU to
accept the interrupt. Acceptance of interrupts is enabled or disabled by software using the interrupt master enable flag
(IMF) and individual enable flag (EF) for each interrupt source. If multiple maskable interrupts are generated simul-
taneously, the interrupts are accepted in order of descending priority. The priorities are determined by the interrupt
priority change control register (ILPRS1-ILPRS8) as Levels and determined by the hardware as the basic priorities.
Internal/Ex-
The TMP89FM82T has a total of 33 interrupt sources excluding reset. Interrupts can be nested with priorities. Three
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and have independent vector
However, there are no prioritized interrupt sources among non-maskable interrupts.
External
External
External
External
External
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
ternal
-
-
(Reset)
INTSWI
INTUNDEF
INTWDT
INTWUC
INTTBT
INTRXD0 / INTSIO0
INTTXD0
INT5
INTVLTD
INTADC
-
INTTC00
INTTC01
INTTCA0
-
INT0
INT1
INT2
INT3
INT4
INTTCA1
INTRXD1
INTTXD1
INTTC02
INTTC03
INTEMG
INTCLM
INTTMR3
INTPDC
INTPWM
INTEDT
INTTMR1
INTTMR2
INTSEI0
Interrupt sources
Non-maskable
Non-maskable
Non-maskable
Non-maskable
IMF AND EIRL<EF4> = 1
IMF AND EIRL<EF5> = 1
IMF AND EIRL<EF6> = 1
IMF AND EIRL<EF7> = 1
IMF AND EIRH<EF8> = 1
IMF AND EIRH<EF9> = 1
IMF AND EIRH<EF10> = 1
-
IMF AND EIRH<EF12> = 1
IMF AND EIRH<EF13> = 1
IMF AND EIRH<EF14> = 1
-
IMF AND EIRE<EF16> = 1
IMF AND EIRE<EF17> = 1
IMF AND EIRE<EF18> = 1
IMF AND EIRE<EF19> = 1
IMF AND EIRE<EF20> = 1
IMF AND EIRE<EF21> = 1
IMF AND EIRE<EF22> = 1
IMF AND EIRE<EF23> = 1
IMF AND EIRD<EF24> = 1
IMF AND EIRD<EF25> = 1
IMF AND EIRD<EF26> = 1
IMF AND EIRD<EF27> = 1
IMF AND EIRD<EF28> = 1
IMF AND EIRD<EF29> = 1
IMF AND EIRD<EF30> = 1
IMF AND EIRD<EF31> = 1
IMF AND EIRC<EF32> = 1
IMF AND EIRC<EF33> = 1
IMF AND EIRC<EF34> = 1
Page 49
Enable condition
ILH<IL10>
ILH<IL12>
ILH<IL13>
ILH<IL14>
ILE<IL16>
ILE<IL17>
ILE<IL18>
ILE<IL19>
ILE<IL20>
ILE<IL21>
ILE<IL22>
ILE<IL23>
ILD<IL24>
ILD<IL25>
ILD<IL26>
ILD<IL27>
ILD<IL28>
ILD<IL29>
ILD<IL30>
ILD<IL31>
ILC<IL32>
ILC<IL33>
ILC<IL34>
ILH<IL8>
ILH<IL9>
ILL<IL3>
ILL<IL4>
ILL<IL5>
ILL<IL6>
ILL<IL7>
Interrupt
latch
-
-
-
-
-
RVCTR=0
0xFFFC
0xFFFC
0xFFEE
0xFFEC
0xFFEA
0xFFDE
0xFFDC
0xFFDA
0xFFCE
0xFFCC
0xFFCA
enabled
0xFFFE
0xFFF8
0xFFF6
0xFFF4
0xFFF2
0xFFF0
0xFFE6
0xFFE4
0xFFE2
0xFFD8
0xFFD6
0xFFD4
0xFFD2
0xFFD0
0xFFC8
0xFFC6
0xFFC4
0xFFC2
0xFFC0
0xFF9E
0xFF9C
0xFF9A
Vector Address
-
-
(MCU mode)
RVCTR=1
enabled
0x01DC
0x01CC
0x01FC
0x01FC
0x01EE
0x01EC
0x01EA
0x01E6
0x01E4
0x01E2
0x01DE
0x01DA
0x01D8
0x01D6
0x01D4
0x01D2
0x01D0
0x01CE
0x01CA
0x01C8
0x01C6
0x01C4
0x01C2
0x01C0
0x019E
0x019C
0x019A
0x01F8
0x01F6
0x01F4
0x01F2
0x01F0
TMP89FM82T
-
-
-
priori-
Basic
10
11
13
14
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
ty
1
2
2
2
5
6
7
8
9
-
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