lh28f800bg-l Sharp Microelectronics of the Americas, lh28f800bg-l Datasheet - Page 20

• Manufacturer Part Number: lh28f800bg-l
• Description: M-bit Smartvoltage Flash Memories
• Manufacturer: Sharp Microelectronics of the Americas

5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Three-
line control provides for :
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 RY/BY#, Block Erase and Word
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase and
word write completion. It transitions low after block
erase or word write commands and returns to V
when the WSM has finished executing the internal
algorithm.
RY/BY# can be connected to an interrupt input of
the system CPU or controller. It is active at all
times. RY/BY# is also V
block erase suspend (with word write inactive),
word write suspend or deep power-down modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics
require
designers are interested in three supply current
issues; standby current levels, active current levels
a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention
will not occur.
Write Polling
careful
device
OH
when the device is in
decoupling.
System
OH
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and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its V
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between V
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4 V
Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the V
trace. The V
for word writing and block erasing. Use similar trace
widths and layout considerations given to the V
power bus. Adequate V
decoupling will decrease V
overshoots.
5.5 V
Block erase and word write are not guaranteed if
V
outside of a valid V
V
is set to "1" along with SR.4 or SR.5, depending on
the attempted operation. If RP# transitions to V
during block erase or word write, RY/BY# will
remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation
is restored. Device power-off or RP# transitions to
V
PP
HH
IL
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
clear the status register.
. If V
falls outside of a valid V
PP
CC
PP
, V
error is detected, status register bit SR.3
Trace on Printed Circuit Boards
PP
CC
PP
pin supplies the memory cell current
, RP# Transitions
and GND and between its V
CC1/2/3/4
PP
PPH1/2/3
range, or RP# ≠ V
PP
supply traces and
voltage spikes and
PP
range, V
power supply
CC
IH
falls
CC
CC
PP
or
IL