w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 55

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

BDLAB = 0
BDLAB = 0
BDLAB = 0
BDLAB = 1
BDLAB = 1
Register Address Base
+ 0
+ 0
+ 1
+ 2
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
+ 0
+ 1
TABLE 4-1 UART Register Bit Map
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Interrupt Control
Buffer Register
Interrupt Status
Status Register
UART Control
User Defined
Divisor Latch
Divisor Latch
UART Status
(Read Only)
(Write Only)
(Read Only)
(Write Only)
Transmitter
UART FIFO
Handshake
Handshake
Receiver
Baudrate
Baudrate
Register
Register
Register
Register
Register
Register
Register
Register
Control
Control
Buffer
Low
High
RBR
TBR
UFR
UCR
HCR
USR
HSR
UDR
BHL
BLL
ICR
ISR
RBR Data
RBR Data
RX Data
TX Data
Interrupt
Interrupt
Terminal
Toggling
(ERDRI)
Pending
Length
(DLS0)
(TCTS)
Ready
Enable
Enable
Ready
Ready
Select
(RDR)
(DTR)
"0" if
Bit 0
Bit 0
FIFO
Data
Bit 0
Data
Bit 0
Bit 0
Bit 8
CTS
0
RX Data
(ETBREI)
Interrupt
Interrupt
Request
Overrun
Toggling
TX Data
(TDSR)
Length
(DLS1)
Enable
Status
Empty
Bit (0)
RCVR
Select
(OER)
Reset
(RTS)
Send
Error
Bit 1
Bit 1
FIFO
Data
Bit 1
DSR
Bit 1
Bit 1
Bit 9
TBR
to
1
Loopback
Stop Bits
Parity Bit
RI Falling
RX Data
Interrupt
TX Data
Interrupt
(EUSRI)
Multiple
(MSBE)
(PBER)
Enable
Status
Enable
Bit (1)
(FERI)
Reset
Bit 10
XMIT
Input
Error
Edge
Bit 2
Bit 2
FIFO
Bit 2
Bit 2
USR
RI
2
- 48 -
Bit Number
RX Data
Interrupt
Interrupt
Toggling
TX Data
(EHSRI)
Bit (2)**
No Stop
(NSER)
(TDCD)
Enable
Status
Enable
Enable
Select
Parity
(PBE)
Bit 11
Mode
DMA
Error
Bit 3
Bit 3
HSR
DCD
Bit 3
Bit 3
IRQ
Bit
Bit
3
Publication Release Date: Nov. 2000
Reserved
Loopback
Detected
RX Data
TX Data
to Send
Internal
Enable
Enable
(SBD)
Parity
(CTS)
Bit 12
(EPE)
Silent
Clear
Even
Bit 4
Bit 4
Byte
Bit 4
Bit 4
4
0
0
Reversed
RX Data
TX Data
Bit Fixed
Data Set
(TBRE)
Enable
Ready
PBFE)
Empty
(DSR)
Parity
Bit 13
Bit 5
Bit 5
Bit 5
Bit 5
TBR
PRELIMINARY
W83627SF
5
0
0
0
Revision 0.60
Active Level
RX Data
Indicator
Interrupt
TX Data
Enabled
Silence
(TSRE)
Enable
Empty
FIFOs
(LSB)
(SSE)
Bit 14
Bit 6
Bit 6
Ring
Bit 6
Bit 6
TSR
(RI)
Set
RX
**
6
0
0
Active Level
Data Carrier
Access Bit
Indication
Baudrate
(BDLAB)
RX Data
Interrupt
RX FIFO
(RFEI) **
TX Data
Enabled
Divisor
Detect
(MSB)
(DCD)
FIFOs
Latch
Bit 15
Error
Bit 7
Bit 7
Bit 7
Bit 7
RX
**
7
0
0