w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 114

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

CR28 (Default 0x00)
CR29 (GPIO3 multiplexed pin selection register. VBAT powered. Default 0x00)
*Note: The falling edge of PWRCTL# signal (pin 72) is delayed an additional 5ms from the falling
Bit 7 - 3 : Reserved.
Bit 2 - 0 : PRTMODS2 - PRTMODS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The corresponding power on setting pin is GP42 (pin 102). Its value is latched on the rising edge of
internal RSMRST# signal (delay of rising edge of Internal RSMRST# signal from VSB on is half way
of that of external RSMRST# pin).
The S3 state power control pin (pin 104) outputs low when VSB is on. It outputs high following the
falling edge of SLP_SX# (pin 73) signal falling edge. Then it is reset by the falling edge of S5# signal
(pin 103).
edge of SLP_SX# signal for supporting STR (Suspend To RAM) function.
= 0xx Parallel Port Mode
= 100 Reserved
= 101 External FDC Mode
= 110 Reserved
= 111 External two FDC Mode
: PIN64S
= 0
= 1
: PIN69S
= 00
= 01
: PIN70S
= 0
= 1
: PIN71S
= 0
= 1
: PIN72S
= 0
= 1
: PIN 73S
= 0
= 1
: Reserved.
: PIN103S
= 0 Pin 103 and pin 104 function as GP41 and GP40 respectively.
=1
Pin 103 is S5# signal input signal and pin 104 is system S3 state power control
SUSLED (SUSLED control bits are in CRF3 of Logical Device 9)
GP35
RSMRST#
GP33
GP32
PWRCTL#
GP31
SLP_SX#
GP30
PWROK
signal.
CIRRX#
GP34
- 107 -
Publication Release Date: Nov. 2000
PRELIMINARY
W83627SF
Revision 0.60