w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 5

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

6. PARALLEL PORT ------------------------------------------------------------------------------------------ 64
6.1 PRINTER INTERFACE LOGIC --------------------------------------------------------------------------------------------------------- 64
6.2 ENHANCED PARALLEL PORT (EPP) ----------------------------------------------------------------------------------------------- 65
6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT -------------------------------------------------------------------------- 70
6.4 EXTENSION FDD MODE (EXTFDD) ------------------------------------------------------------------------------------------------ 78
5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) ----------------------------------------------------------------------- 61
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ------------------------------------------------------------------- 62
5.1.10 Bank1.Reg2 - Version ID Regiister I (VID)--------------------------------------------------------------------------------- 63
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)-------------------- 63
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL) -------------------------------------------------------------------------- 63
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH) ------------------------------------------------------------------------ 63
6.2.1 Data Swapper------------------------------------------------------------------------------------------------------------------------ 66
6.2.2 Printer Status Buffer---------------------------------------------------------------------------------------------------------------- 66
6.2.3 Printer Control Latch and Printer Control Swapper--------------------------------------------------------------------- 67
6.2.4 EPP Address Port ------------------------------------------------------------------------------------------------------------------- 67
6.2.5 EPP Data Port 0-3 ------------------------------------------------------------------------------------------------------------------ 68
6.2.6 Bit Map of Parallel Port and EPP Registers -------------------------------------------------------------------------------- 68
6.2.7 EPP Pin Descriptions-------------------------------------------------------------------------------------------------------------- 69
6.2.8 EPP Operation----------------------------------------------------------------------------------------------------------------------- 69
6.3.1 ECP Register and Mode Definitions------------------------------------------------------------------------------------------- 70
6.3.2 Data and ecpAFifo Port----------------------------------------------------------------------------------------------------------- 71
6.3.3 Device Status Register (DSR)---------------------------------------------------------------------------------------------------- 71
6.3.4 Device Control Register (DCR) ------------------------------------------------------------------------------------------------- 72
6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ------------------------------------------------------------------------------ 73
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 ------------------------------------------------------------------------------------ 73
6.3.7 tFifo (Test FIFO Mode) Mode = 110 ------------------------------------------------------------------------------------------ 73
6.3.8 cnfgA (Configuration Register A) Mode = 111----------------------------------------------------------------------------- 73
6.3.9 cnfgB (Configuration Register B) Mode = 111----------------------------------------------------------------------------- 73
6.3.10 ecr (Extended Control Register) Mode = all------------------------------------------------------------------------------ 74
6.3.11 Bit Map of ECP Port Registers ------------------------------------------------------------------------------------------------ 75
6.3.12 ECP Pin Descriptions------------------------------------------------------------------------------------------------------------ 76
6.3.13 ECP Operation--------------------------------------------------------------------------------------------------------------------- 77
6.3.14 FIFO Operation-------------------------------------------------------------------------------------------------------------------- 77
6.3.15 DMA Transfers --------------------------------------------------------------------------------------------------------------------- 78
6.3.16 Programmed I/O (NON-DMA) Mode----------------------------------------------------------------------------------------- 78
-III -
Publication Release Date: Nov. 2000
W83627SF
P R E L I M I N A R Y
Revision 0.60