w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 127

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

CRF3 (MIDI FIFO Threshold register. Default 0x00)
Bit 7 - 6: MIDI FIFO Threshold.
Bit 5-0: Reserved
13.9 Logical Device 8 (GPIO Port 2)
CR30 (GP20-GP27 Default 0x00)
CR60, CR 61 (Default 0x00, 0x00)
CRF0 (GP20-GP27 I/O selection register. Default 0xFF)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.
CRF1 (GP20-GP27 data register. Default 0x00)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.
CRF2 (GP20-GP27 inversion register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.
CRF3 (Default 0x00)
CRF4 (Reserved)
note: bit 0 is initialized to power on setting value of pin 81 on the rising edge of PWROK.
These two registers select GP2 I/O base address [0x100:0xFF8] on 1 byte boundary.
Bit 7 - 1 : Reserved.
Bit 0
Bit 7 - 4 : These bits select IRQ resource for IRQIN1.
Bit 3 - 0 : These bits select IRQ resource for IRQIN0.
BIT 7
0
0
1
1
= 1 Activate GPIO2.
= 0 GPIO2 is inactive.
BIT 6
0
1
0
1
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
- 120 -
01
04
08
14
Publication Release Date: Nov. 2000
PRELIMINARY
W83627SF
Revision 0.60