mpc7450 Freescale Semiconductor, Inc, mpc7450 Datasheet - Page 37

• Manufacturer Part Number: mpc7450
• Description: Mpc7450 Risc Microprocessor
• Manufacturer: Freescale Semiconductor, Inc

The MPC7450 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock
frequency of the MPC7450. The core-to-L3 frequency divisor for the L3 PLL is selected through the
L3_CLK bits of the L3CR register. Generally, the divisor must be chosen according to the frequency
supported by the external RAMs, the frequency of the MPC7450 core, and timing analysis of the circuit
board routing. Table 17 shows various example L3 clock frequencies that can be obtained for a given set of
core frequencies.
MOTOROLA
Notes:
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.
4. In PLL-off mode, no clocking occurs inside the MPC7450 regardless of the SYSCLK input.
PLL_EXT
Core Frequency (MHz)
Table 16. MPC7450 Microprocessor PLL Configuration Example for 600 MHz Parts (continued)
or VCO frequencies which are not useful, not supported, or not tested for by the MPC7450; see Section 1.5.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must
be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup t
time t
internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use
only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
1
1
1
1
1
1
1
1
0
0
IXKH
500
533
PLL_CFG
(see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK while the
0111
1010
1001
1011
0101
1100
0001
1101
0011
1111
[0:3]
Multiplier
MPC7450 RISC Microprocessor Hardware Specifications
Bus-to-
Core
10x
11x
12x
13x
14x
15x
16x
PLL off/bypass
9x
Freescale Semiconductor, Inc.
250
266
PLL off
÷2
For More Information On This Product,
Table 17. Sample Core-to-L3 Frequencies
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Multiplier
Core-to-
VCO
2x
2x
2x
2x
2x
2x
2x
2x
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÷2.5
200
213
33.3 MHz
(1000)
(1066)
(600)
(666)
(733)
(866)
(933)
(800
Bus
300
333
366
400
433
466
500
533
167
178
÷3
50 MHz
(1000)
(1100)
(1200)
(1300)
(1400)
(1500)
PLL off, SYSCLK clocks core circuitry directly
(900)
Bus
450
500
550
600
650
700
750
PLL off, no core clocking occurs
66.6 MHz
(1200)
(1333)
(1466)
÷3.5
143
152
Bus
600
667
733
75 MHz
(1350)
(1500)
Bus
675
750
125
133
÷4
System Design Information
83 MHz
(1494)
Bus
747
100
107
100 MHz
÷5
Bus
IVKH
133 MHz
and hold
83
89
Bus
÷6
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