mpc7450 Freescale Semiconductor, Inc, mpc7450 Datasheet - Page 27

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mpc7450

Manufacturer Part Number
mpc7450
Description
Mpc7450 Risc Microprocessor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Figure 12 shows the L3 bus timing diagrams for the MPC7450 interfaced to PB2 or Late Write SRAMs.
1.5.2.5
Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14, Figure 15,
Figure 16, and Figure 17.
MOTOROLA
At recommended operating conditions. See Table 4.
TCK frequency of operation
TCK cycle time
TCK clock pulse width measured at 1.4 V
TCK rise and fall times
TRST assert time
Input setup times:
Input hold times:
Boundary-scan data
TMS, TDI
Boundary-scan data
TMS, TDI
Outputs
Inputs
L3_ECHO_CLK[0,2]
L3_ECHO_CLK[1,3]
L3 Data and Data
ADDR, L3_CNTL
L3DATA WRITE
Parity Inputs
L3_CLK[0,1]
IEEE 1149.1 AC Timing Specifications
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK)
Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
Parameter
MPC7450 RISC Microprocessor Hardware Specifications
Freescale Semiconductor, Inc.
For More Information On This Product,
VM
t
t
L3CHOV
L3CHDV
VM = Midpoint Voltage (GV
Go to: www.freescale.com
t
JR
Symbol
t
t
t
f
t
t
t
t
TRST
DXJH
TCLK
DVJH
TCLK
JHJL
and t
IVJH
IXJH
VM
VM
t
L3DVEH
JF
DD
t
/2)
Electrical and Thermal Characteristics
L3DXEH
Min
30
15
25
20
25
0
0
4
0
t
t
L3CHOX
L3CHDX
t
L3CHOZ
t
L3CHDZ
Max
33.3
2
1
MHz
Unit
ns
ns
ns
ns
ns
ns
Notes
2
3
3
27

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