mpc7450 Freescale Semiconductor, Inc, mpc7450 Datasheet
mpc7450
Related parts for mpc7450
mpc7450 Summary of contents
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... L2, and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high bandwidth interface. Figure 1 shows a block diagram of the MPC7450. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources ...
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... Freescale Semiconductor, Inc. Overview Figure 1. MPC7450 Block Diagram 2 MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. 1.2 Features This section summarizes features of the MPC7450 implementation of the PowerPC architecture. Major features of the MPC7450 are as follows: Major features of the MPC7450 are as follows: • High-performance, superscalar microprocessor — As many as 4 instructions can be fetched from the instruction cache at a time — ...
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... Guarantees sequential programming model (precise exception model) — Monitors all dispatched instructions and retires them in order 4 MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... Private memory capability for half (1-Mbyte minimum) or all of the L3 SRAM space — Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined synchronous Burst SRAMs, and pipelined (register-register) Late Write synchronous Burst SRAMs MOTOROLA MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, Go to: www.freescale.com Features 5 ...
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... PLL in a locked and running state. All internal functional units are disabled. – Deep sleep—When the part is in the sleep state, the system can disable the PLL resulting. 6 MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, Go to: www.freescale.com ...
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... Comparison with the MPC7400 Table 1 compares the key features of the MPC7450 with the key features of the earlier MPC7400. To achieve a higher frequency, the number of logic levels per cycle is reduced. Also, to achieve this higher frequency, the pipeline of the MPC7450 is extended (compared to the MPC7400), while maintaining the same level of performance as measured by the number of instructions executed per cycle (IPC) ...
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... Associativity Locking Granularity/Style Parity on I Cache Parity on D Cache Number of D Cache Misses (Load/Store) Data Stream Touch Engines Cache Level 8 MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, MPC7450 1 Entry 3 Queues In Order, 4 Queues In Order Branch Processing Resources BTIC, BHT, Link Stack ...
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... Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7450. 1.5.1 DC Electrical Characteristics The tables in this section describe the MPC7450 DC electrical characteristics. Table 2 provides the absolute maximum ratings. MOTOROLA MPC7450 RISC Microprocessor Hardware Specifications ...
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... L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5 V mode. 9. L3VSEL must be set to 0, such that the bus is in 1.8 V mode. 10. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5 V mode. 10 MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, 1 Symbol ...
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... Figure 2. Overshoot/Undershoot Voltage The MPC7450 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The MPC7450 core voltage must always be provided at nominal 1.6 V (see Table 4 for actual recommended core voltage). Voltage to the L3 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET ...
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... Freescale Semiconductor, Inc. Electrical and Thermal Characteristics Table 4 provides the recommended operating conditions for the MPC7450. Table 4. Recommended Characteristic Core supply voltage PLL supply voltage Processor bus supply voltage BVSEL = 0 BVSEL = HRESET bus supply voltage L3VSEL = 0 L3VSEL = HRESET or GV L3VSEL = ¬HRESET ...
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... Freescale Semiconductor, Inc. Table 6 provides the DC electrical characteristics for the MPC7450. Table 6. DC Electrical Specifications At recommended operating conditions. See Table 4. Nominal Characteristic Voltage Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage ...
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... AC Electrical Characteristics This section provides the AC electrical characteristics for the MPC7450. After fabrication, functional parts are sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Specifications,” and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_EXT and PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency ...
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... KHKL Figure 3. SYSCLK Input Timing Diagram 1.5.2.2 Processor Bus AC Specifications Table 9 provides the processor bus AC timing specifications for the MPC7450 as defined in Figure 4 and Figure 5. Timing specifications for the L3 bus are provided in Section 1.5.2.3, “L3 Clock AC Specifications.” MOTOROLA MPC7450 RISC Microprocessor Hardware Specifi ...
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... BR, CKSTP_OUT, DRDY, HIT, PMON_OUT, QREQ SYSCLK to output enable SYSCLK to output high impedance (all except TS, ARTRY, SHD0, SHD1) SYSCLK to TS high impedance after precharge Maximum delay to ARTRY/SHD0/SHD1 precharge 16 MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, All Speed Grades 2 Symbol Min t ...
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... The nominal precharge width for SHD0 and SHD1 is 1.0 t sysclk core to bus (PLL configurations). 10. Guaranteed by design and not tested. Figure 4 provides the AC test load for the MPC7450. Output MOTOROLA MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, ...
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... Freescale Semiconductor, Inc. Electrical and Thermal Characteristics Figure 5 provides the mode select input timing diagram for the MPC7450. HRESET Mode Signals Figure 5. Mode Input Timing Diagram Figure 6 provides the input/output timing diagram for the MPC7450. SYSCLK VM All Inputs All Outputs (Except TS, ...
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... Table 10 is considered to be the practical maximum in a typical system. The maximum L3_CLK frequency for any application of the MPC7450 will be a function of the AC timings of the MPC7450, the AC timings for the SRAM, bus loading, and printed circuit board trace length. ...
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... Figure 8. AC Test Load for the L3 Interface In general, if routing is short, delay-matched, and designed for incident wave reception and minimal reflection, there is a high probability that the AC timing of the MPC7450 L3 interface will meet the maximum frequency operation of appropriately chosen SRAMs. This is despite the pessimistic, guard-banded AC specifi ...
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... L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address, control, data, and L3_CLKn signals have propagated across the printed wiring board. Inputs to the MPC7450 are source-synchronous with the CQ clock generated by the DDR MSUG2 SRAMs. These CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7450. An internal circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data window at the internal receiving latches ...
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... L3_ECHO_CLKn. This parameter indicates that the MPC7450 can latch L3_ECHO_CLK an input signal that is valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency. 5. All output specifi ...
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... Freescale Semiconductor, Inc. Figure 9 shows the typical connection diagram for the MPC7450 interfaced to MSUG2 SRAMs such as the Motorola MCM64E836. MPC7450 Denotes L3_ECHO_CLK[0] Receive (SRAM {L3DATA[0:15], to MPC7450) Aligned Signals {L3DATA[16:31], L3_ECHO_CLK[1] Denotes Transmit (MPC7450 to SRAM) Aligned Signals {L3_DATA[32:47], {L3DATA[48:63], Figure 9. Typical Source Synchronous 2-Mbyte L3 Cache DDR Interface MOTOROLA MPC7450 RISC Microprocessor Hardware Specifi ...
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... L3_ECHO_CLK3 must be routed halfway to the SRAMs and then returned to the MPC7450 inputs L3_ECHO_CLK0 and L3_ECHO_CLK2 respectively. Thus, L3_ECHO_CLK0 and L3_ECHO_CLK2 are phase-aligned with the input clock received at the SRAMs. The MPC7450 will latch the incoming data on the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2. ...
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... SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled. 5. Timing behavior and characterization are currently being evaluated. MOTOROLA MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, Electrical and Thermal Characteristics All Speed Grades ...
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... Freescale Semiconductor, Inc. Electrical and Thermal Characteristics Figure 11 shows the typical connection diagram for the MPC7450 interfaced to PB2 SRAMs, such as the Motorola MCM63R737, or Late Write SRAMs, such as the Motorola MCM63R836A. MPC7450 Denotes Receive (SRAM to MPC7450) Aligned Signals {L3_DATA[16:31], Denotes Transmit (MPC7450 to ...
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... Freescale Semiconductor, Inc. Figure 12 shows the L3 bus timing diagrams for the MPC7450 interfaced to PB2 or Late Write SRAMs. Outputs L3_CLK[0,1] VM L3_ECHO_CLK[1,3] ADDR, L3_CNTL L3DATA WRITE Inputs L3_ECHO_CLK[0,2] Parity Inputs L3 Data and Data Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs 1.5.2.5 IEEE 1149.1 AC Timing Specifi ...
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... Non-JTAG signal input timing with respect to TCK. 4. Non-JTAG signal output timing with respect to TCK. 5. Guaranteed by design and characterization. Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7450. Output Figure 13. Alternate AC Test Load for the JTAG Interface Figure 14 provides the JTAG clock input timing diagram. ...
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... Figure 17 provides the test access port timing diagram. TCK VM TDI, TMS TDO TDO Output Data Valid Figure 17. Test Access Port Timing Diagram MOTOROLA MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, Electrical and Thermal Characteristics VM t DVJH t JLDV t ...
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... Freescale Semiconductor, Inc. Pin Assignments 1.6 Pin Assignments Figure 18 (in Part A) shows the pinout of the MPC7450, 483 CBGA package as viewed from the top surface. Part B shows the side profile of the CBGA package to indicate the direction of the top surface view. Part ...
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... Freescale Semiconductor, Inc. 1.7 Pinout Listings for the 483 CBGA Package Table 15 provides the pinout listing for the MPC7450, 483 CBGA package. Table 15. Pinout Listing for the MPC7450, 483 CBGA Package Signal Name A[0:35] E10, N4, E8, N5, C8, R2, A7, M2, A6, M1, A10, U2, N2, P8, M8, W4, N6, U6, R5, Y4, ...
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... Freescale Semiconductor, Inc. Pinout Listings for the 483 CBGA Package Table 15. Pinout Listing for the MPC7450, 483 CBGA Package (continued) Signal Name GND A22, B1, B5, B12, B14, B16, B18, B20, C3, C9, C21, D7, D13, D15, D17, D19, E2, E5, E21, F10, F12, F14, F16, F19, G4, G7, G17, ...
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... Freescale Semiconductor, Inc. Table 15. Pinout Listing for the MPC7450, 483 CBGA Package (continued) Signal Name OV B3, C5, C7, C10, D2, E3, E9, F5, G3, G9, H7, DD J5, K3, L7, M5, N3, P7, R4, T3, U5, U7, U11, U15, V3, V9, V13, Y2, Y5, Y7, Y10, Y17, Y19, AA4, AA15 PLL_CFG[0:3] A2, F7, C2, D4 PLL_EXT ...
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... This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance. 13. These signals must be pulled down to GND if unused or if the MPC7450 is in 60x bus mode. 14. This signal must be asserted during reset, by pull-down to GND or assertion by HRESET, to ensure proper operation ...
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... Freescale Semiconductor, Inc. 1.8.2 Mechanical Dimensions for the MPC7450, 483 CBGA Figure 19 provides the mechanical dimensions and bottom surface nomenclature for the MPC7450, 483 CBGA package CORNER ...
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... The PLL configuration for the MPC7450 is shown in Table 16 for a set of example frequencies. In this example, shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 600-MHz column in Table 8. Table 16. MPC7450 Microprocessor PLL Confi ...
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... The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the MPC7450; see Section 1.5.2.1, “Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies. ...
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... The core and L3 frequencies are for reference only. Some examples may represent core or L3 frequencies which are not useful, not supported, or not tested for the MPC7450; see Section 1.5.2.3, “L3 Clock AC Specifications,” for valid L3_CLK frequencies. (Shaded cells do not comply with Table 10.) 2. These core frequencies are not supported by all speed grades ...
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... Decoupling Recommendations Due to the MPC7450 dynamic power management feature, large address and data buses, and high operating frequencies, the MPC7450 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC7450 system, and the MPC7450 itself requires a clean, tightly regulated source of power ...
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... Pull-Up/Pull-Down Resistor Requirements The MPC7450 requires high-resistive (weak: 4 pull-up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC7450 or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1. ...
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... A[0:35], AP[0:4], TT[0:4], CI, WT, and GBL. If extended addressing is not used, A[0:3] are unused and must be be pulled low to GND through weak pull-down resistors. If the MPC7450 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak pull-down resistors. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus ...
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... The QACK signal shown in Figure 23 is usually connected to the PCI bridge chip in a system and is an input to the MPC7450 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the MPC7450 must see this signal asserted (pulled down) ...
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... Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7450. Connect pin 5 of the COP header Key location; Pin 14 is not physically present on the COP header Component not populated. Populate only if JTAG interface is unused. 4. Component not populated. Populate only if debug tool does not drive QACK. ...
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... Thermal Interface Material Figure 24. Package Exploded Cross-Sectional View with Several Heat Sink Options The board designer can choose between several types of heat sinks to place on the MPC7450. There are several commercially available heat sinks for the MPC7450 provided by the following vendors: Chip Coolers Inc. ...
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... A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 26 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, MOTOROLA MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, 905-760-1992 Radiation ...
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... Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 24). Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure and is recommended due to the high power dissipation of the MPC7450. Of course, the selection of any thermal interface material depends on many factors—thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc ...
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... Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, MOTOROLA MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, 888-246-9050 860-571-5100 ...
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... Removed 25 MHz column from Table 16 and added 83 MHz column. Changed all references to inverted HRESET from HRESET to ¬HRESET for clarity and to be consistent with the MPC7450 RISC Microprocessor Family User’s Manual. Moved Table 11 (Table 13 in prior revisions) to Section 1.5.2.4, “L3 Bus AC Specifications” because these specifications apply to all supported SRAM types, added specifi ...
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... Part Numbers Fully Addressed by This Document Table 20 provides the Motorola part numbering nomenclature for the MPC7450. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifi ...
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... ATWLYYWWA is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States. Figure 27. Part Marking for BGA Device 50 MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, Document Order Number of Operating Conditions Applicable Specification 1.8 V ± ...
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... Freescale Semiconductor, Inc. MOTOROLA MPC7450 RISC Microprocessor Hardware Specifications For More Information On This Product, Go to: www.freescale.com Ordering Information 51 ...
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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2001 MPC7450EC/D For More Information On This Product, Go to: www.freescale.com ...