mpc7450 Freescale Semiconductor, Inc, mpc7450 Datasheet - Page 28

no-image

mpc7450

Manufacturer Part Number
mpc7450
Description
Mpc7450 Risc Microprocessor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Electrical and Thermal Characteristics
Figure 13 provides the AC test load for TDO and the boundary-scan outputs of the MPC7450.
Figure 14 provides the JTAG clock input timing diagram.
Figure 15 provides the TRST timing diagram.
At recommended operating conditions. See Table 4.
Valid times:
Output hold times:
TCK to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
28
Boundary-scan data
TDO
Boundary-scan data
TDO
Boundary-scan data
TDO
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
(see Figure 13). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
TCLK
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK)
TRST
Parameter
Output
Figure 13. Alternate AC Test Load for the JTAG Interface
MPC7450 RISC Microprocessor Hardware Specifications
VM
Freescale Semiconductor, Inc.
VM
Figure 14. JTAG Clock Input Timing Diagram
t
JHJL
For More Information On This Product,
VM = Midpoint Voltage (OV
Figure 15. TRST Timing Diagram
t
TCLK
VM = Midpoint Voltage (OV
Go to: www.freescale.com
VM
Z
0
= 50
t
TRST
VM
Symbol
t
t
t
t
t
t
JLOV
JLDX
JLOX
JLOZ
JLDV
JLDZ
DD
/2)
DD
VM
R
/2)
L
TBD
TBD
t
Min
= 50
JR
4
4
3
3
Max
TBD
TBD
OV
20
25
19
9
DD
1
(continued)
/2
Unit
ns
ns
ns
t
JF
MOTOROLA
Notes
load
4, 5
4
4
5

Related parts for mpc7450