mpc7450 Freescale Semiconductor, Inc, mpc7450 Datasheet - Page 34

• Manufacturer Part Number: mpc7450
• Description: Mpc7450 Risc Microprocessor
• Manufacturer: Freescale Semiconductor, Inc

Package Description
1.8
The following sections provide the package parameters and mechanical dimensions for the CBGA package.
1.8.1
The package parameters are as provided in the following list. The package type is 29
ceramic ball grid array (CBGA).
34
V
Notes:
1. OV
2. These input signals are for factory use only and must be pulled up to OV
3. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to HRESET
4. Ignored in 60x bus mode.
5. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at
6. This signal must be negated during reset, by pull-up to OV
7. Internal pull-up on die.
8. These pins require weak pull-up resistors (for example, 4.7 k ) to maintain the control signals in the negated
9. These input signals for factory use only and must be pulled down to GND for normal machine operation.
10. This pin can externally enable the performance monitor counters (PMC) if they are internally enabled by the
11. Unused address pins must be pulled down to GND.
12. This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect
13. These signals must be pulled down to GND if unused or if the MPC7450 is in 60x bus mode.
14. This signal must be asserted during reset, by pull-down to GND or assertion by HRESET, to ensure proper
15. Power must be supplied to GV
DD
Signal Name
(L3CTL[0:1]); GV
L3_ECHO_CLK[0:3], and L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and V
processor core and the PLL (after filtering to become AV
voltages, see Table 4.
(selects 2.5 V). To program the L3 interface, connect L3VSEL to either GND (selects 1.8 V) or to HRESET
(selects 2.5 V) or to HRESET (selects 1.5 V). If used, pulldown resistors should be less than 250
HRESET going high.
ensure proper operation.
state after they have been actively negated and released by the MPC7450 and other bus masters.
software. If it will not be used to control the PMC, it should be pulled down to GND so that the software can
enable the PMC.
performance.
operation.
DD
Package outline
Interconnects
Pitch
Minimum module height
Maximum module height
Ball diameter
supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls
Package Description
Package Parameters for the MPC7450, 483 CBGA
Table 15. Pinout Listing for the MPC7450, 483 CBGA Package (continued)
DD
J9, J11, J13, J15, K10, K12, K14, L9, L11,
L13, L15, M10, M12, M14, N9, N11, N13,
N15, P10, P12, P14
supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7],
MPC7450 RISC Microprocessor Hardware Specifications
Freescale Semiconductor, Inc.
For More Information On This Product,
DD
, even when the L3 interface is disabled or unused.
Pin Number
Go to: www.freescale.com
29
483 (22
1.27 mm (50 mil)
—
3.22 mm
0.89 mm (35 mil)
DD
DD
). For actual recommended value of V
29 mm
or negation by ¬HRESET (inverse of HRESET), to
22 ball array – 1)
Active
—
DD
for normal machine operation.
I/O
—
DD
I/F Select
supplies power to the
N/A
29 mm, 483-lead
in
or supply
1
.
MOTOROLA
Notes