mpc7450 Freescale Semiconductor, Inc, mpc7450 Datasheet - Page 22

• Manufacturer Part Number: mpc7450
• Description: Mpc7450 Risc Microprocessor
• Manufacturer: Freescale Semiconductor, Inc

Electrical and Thermal Characteristics
Table 12 provides the L3 bus interface AC timing specifications for the configuration as shown in Figure 9,
assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8.
At recommended operating conditions. See Table 4.
L3_CLK rise and fall time
Setup times:Data and parity
Input hold times:Data and parity
Valid times:Data and parity
Output hold times:
L3_CLK to high impedance:
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency
4. t
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10. For consistency with other
7. t
22
All other outputs
Data and parity
All other outputs
of the rising or falling edge of the input L3_ECHO_CLKn (see Figure 10). Input timings are measured at the pins.
with other input setup time specifications, this will be treated as negative input setup time.
an input signal that is valid for only a short time before and a short time after the midpoint between the rising and
falling (or falling and rising) edges of L3_ECHO_CLKn at any frequency.
falling) edge of L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All
output timings assume a purely resistive 50-
output valid time specifications, this will be treated as negative output valid time.
launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output
valid and output hold times such that the specified output signal will be valid for approximately one L3_CLK period
starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock
period after the edge it will be sampled.
L3_ECHO_CLK
L3_CLK
/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually
Parameter
/4 is one-fourth the period of L3_ECHO_CLKn. This parameter indicates that the MPC7450 can latch
All other outputs
Data and parity
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2
MPC7450 RISC Microprocessor Hardware Specifications
Freescale Semiconductor, Inc.
For More Information On This Product,
t
t
t
t
L3CHDX
L3DXEH
L3CHDV
L3DVEH
t
L3CR
Go to: www.freescale.com
Symbol
t
t
t
t
L3CHOV
L3CHOX
L3CHOZ
L3CLDZ
and t
and t
and t
and t
and t
load (see Figure 8).
L3CF
L3DVEL
L3DXEL
L3CLDV
L3CLDX
–(t
t
t
t
L3_CLK
L3_ECHO_CLK
L3_CLK
L3_ECHO_CLK
– 0.35)
+ 0.35
Min
—
—
—
—
—
/4 – 0.35
All Speed Grades
/4 + 0.5
/4
/4
–t
t
t
DD
L3_CLK
L3_CLK
L3_CLK
t
.
L3_CLK
Max
1.0
—
—
—
—
/4 + 1.0
/4 + 2.0
/4 + 0.5
/2
Unit
ns
ns
ns
ns
ns
ns
MOTOROLA
Notes
2, 3, 4
5, 6, 7
5, 6, 7
2, 4
5, 7
5, 7
1