cp3ub26 National Semiconductor Corporation, cp3ub26 Datasheet - Page 59

• Manufacturer Part Number: cp3ub26
• Description: Reprogrammable Connectivity Processor With Usb And Can Interfaces
• Manufacturer: National Semiconductor Corporation

12.3
In Idle mode, the System Clock is disabled and therefore the
clock is stopped to most modules of the device. The PLL
and the high-frequency oscillator may be disabled as con-
trolled by register bits. The low-frequency oscillator remains
active. The Power Management Module (PMM) and the
Timing and Watchdog Module (TWM) continue to operate
off the Slow Clock. Auxiliary Clocks 1 and 2 can be turned
off under software control before switching to a power sav-
ing mode, or they remain active as long as Main Clock is
also active. Alternatively, the 12 MHz Main Clock and the
PLL can also be controlled by the Hardware Clock Control
function, if enabled.
12.4
In Halt mode, all the device clocks, including the System
Clock, Main Clock, and Slow Clock, are disabled. The high-
frequency oscillator and PLL are turned off. The low-fre-
quency oscillator continues to operate, however its circuitry
is optimized to guarantee lowest possible power consump-
tion. This mode allows the device to reach the absolute min-
imum power consumption without losing its state (memory,
registers, etc.).
12.5
Altogether, two mechanisms control whether the high-fre-
quency oscillator is active, and three mechanisms control
whether the PLL is active:
! Disable Bits: The DMC and DHC bits in the PMMCR
! Power Management Mode: Halt mode disables the
! PLL Power Down Bit: The PLLPWD bit in the CRCTRL
register may be used to disable the high-frequency oscil-
lator and PLL, respectively, in Power Save and Idle
modes. When used to disable the high-frequency oscilla-
tor or PLL, the DMC and DHC bits override the HCC
mechanism.
high-frequency oscillator and PLL. Active Mode enables
them. The DMC and DHC bits and the HCC mechanism
have no effect in Active or Halt mode.
register can be used to disable the PLL in all modes. This
bit does not affect the high-frequency oscillator.
IDLE MODE
HALT MODE
HIGH-FREQUENCY OSCILLATOR AND
PLL CONTROL
59
12.6
Table 26 lists the power management registers.
12.6.1
The Power Management Control/Status Register (PMMCR)
is a byte-wide, read/write register that controls the operating
power mode (Active, Power Save, Idle, or Halt) and enables
or disables the high-frequency oscillator in the Power Save
and Idle modes. At reset, the non-reserved bits of this reg-
ister are cleared. The format of the register is shown below.
PSM
IDLE
Reserved
7
PMMCR
PMMSR
Name
Table 26 Power Management Registers
Power Management Control Register (PMMCR)
POWER MANAGEMENT REGISTERS
6
If the Power Save Mode bit is clear and the
WBPSM bit is clear, writing 1 to the PSM bit
causes the device to start the switch to Power
Save mode. If the WBPSM bit is set when the
PSM bit is written with 1, entry into Power
Save mode is delayed until execution of a
WAIT instruction. The PSM bit becomes set
after the switch to Power Save mode is com-
plete. The PSM bit can be cleared by soft-
ware, and it can be cleared by hardware when
a hardware wake-up event is detected.
0
1
The Idle Mode bit indicates whether the de-
vice has entered Idle mode. The WBPSM bit
must be set to enter Idle mode. When the
IDLE bit is written with 1, the device enters
IDLE mode at the execution of the next WAIT
instruction. The IDLE bit can be set and
cleared by software. It is also cleared by the
hardware when a hardware wake-up event is
detected.
0
1
–
–
–
–
DHC DMC WBPSM HALT IDLE PSM
Device is not in Power Save mode.
Device is in Power Save mode.
Device is not in Idle mode.
Device is in Idle mode.
5
FF FC60h
FF FC62h
Address
4
3
Power Management
Power Management
Control Register
Status Register
Description
2
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