cp3ub26 National Semiconductor Corporation, cp3ub26 Datasheet - Page 49

• Manufacturer Part Number: cp3ub26
• Description: Reprogrammable Connectivity Processor With Usb And Can Interfaces
• Manufacturer: National Semiconductor Corporation

10.3.4
The IENAM0 register is a word-wide read/write register
which holds bits that individually enable and disable the
maskable interrupt sources IRQ1 through IRQ15. The reg-
ister is initialized to FFFFh at reset.
IENA
10.3.5
The IENAM1 register is a word-wide read/write register
which holds bits that individually enable and disable the
maskable interrupt sources IRQ16 through IRQ31. The reg-
ister is initialized to FFFFh at reset.
IENA
10.3.6
The IENAM2 register is a word-wide read/write register
which holds bits that individually enable and disable the
maskable interrupt sources IRQ32 through IRQ47. The reg-
ister is initialized to FFFFh at reset.
IENA
15
15
15
Interrupt Enable and Mask Register 0 (IENAM0)
Interrupt Enable and Mask Register 1 (IENAM1)
Interrupt Enable and Mask Register 2 (IENAM2)
Each Interrupt Enable bit enables or disables
the corresponding interrupt request IRQ1
through IRQ15, for example IENA15 controls
IRQ15. Because IRQ0 is not used, IENA0 is
ignored.
0
1
Each Interrupt Enable bit enables or disables
the corresponding interrupt request IRQ16
through IRQ31, for example IENA31 controls
IRQ31.
0
1
Each Interrupt Enable bit enables or disables
the corresponding interrupt request IRQ32
through IRQ47, for example IENA47 controls
IRQ47.
0
1
–
–
–
–
–
–
Interrupt is disabled.
Interrupt is enabled.
Interrupt is disabled.
Interrupt is enabled.
Interrupt is disabled.
Interrupt is enabled.
IENA
IENA
IENA
1
Res.
0
0
0
49
10.3.7
The ISTAT0 register is a word-wide read-only register. It in-
dicates which maskable interrupt inputs to the ICU are ac-
tive. These bits are not affected by the state of the
corresponding IENA bits.
IST
10.3.8
The ISTAT1 register is a word-wide read-only register. It in-
dicates which maskable interrupt inputs into the ICU are ac-
tive. These bits are not affected by the state of the
corresponding IENA bits.
IST
10.3.9
The ISTAT2 register is a word-wide read-only register. It in-
dicates which maskable interrupt inputs into the ICU are ac-
tive. These bits are not affected by the state of the
corresponding IENA bits.
IST
15
15
15
Interrupt Status Register 0 (ISTAT0)
Interrupt Status Register 1 (ISTAT1)
Interrupt Status Register 2 (ISTAT2)
The Interrupt Status bits indicate if a
maskable interrupt source is signalling an in-
terrupt request. IST15:1 correspond to IRQ15
to IRQ1 respectively. Because the IRQ0 inter-
rupt is not used, bit 0 always reads back 0.
0
1
The Interrupt Status bits indicate if a
maskable interrupt source is signalling an in-
terrupt request. IST31:16 correspond to
IRQ31 to IRQ16, respectively.
0
1
The Interrupt Status bits indicate if a
maskable interrupt source is signalling an in-
terrupt request. IST47:32 correspond to
IRQ47 to IRQ32, respectively.
0
1
–
–
–
–
–
–
Interrupt is not active.
Interrupt is active.
Interrupt is not active.
Interrupt is active.
Interrupt is not active.
Interrupt is active.
IST
IST
IST
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1
Res.
0
0
0