cp3ub26 National Semiconductor Corporation, cp3ub26 Datasheet - Page 119

• Manufacturer Part Number: cp3ub26
• Description: Reprogrammable Connectivity Processor With Usb And Can Interfaces
• Manufacturer: National Semiconductor Corporation

18.6.4
The transmission process can be started after software has
loaded the buffer registers (data, ID, DLC, PRI) and set the
buffer status from TX_NOT_ACTIVE to TX_ONCE,
TX_RTR, or TX_ONCE_RTR.
When the CPU writes TX_ONCE, the buffer will be
TX_BUSY as soon as the CAN module has scheduled this
buffer for the next transmission. After the frame could be
successfully transmitted, the buffer status will be automati-
cally reset to TX_NOT_ACTIVE when a data frame was
transmitted or to RX_READY when a remote frame was
transmitted.
18.7
The CAN module has one dedicated ICU interrupt vector for
all interrupt conditions. In addition, the data frame receive
event is an input to the MIWU (see Section 13.0). The inter-
rupt process can be initiated from the following sources.
! CAN data transfer
— Reception of a valid data frame in the buffer. (Buffer
— Successful transmission of a data frame. (Buffer state
state changes from RX_READY to RX_FULL or
RX_OVERRUN.)
changes from TX_ONCE to TX_NOT_ACTIVE or
RX_READY.)
TX Buffer States
INTERRUPTS
RTR
received
transmit failed
TX_ONCE_RTR
TX_BUSY2
RX_READY
TX_RTR
1110
1111
1010
0010
CAN
schedules TX
TX done
Figure 48. Transmit Buffer States
Remote transmission
request sent - now wait
to receive a data frame
TX request delayed
by a TX request of higher
priority message
CPU writes 1010
119
Transmit
request cancelled
CPU writes 1000
TX_ONCE
If
TX_ONCE_RTR, it will transmit its data contents. During the
transmission, the buffer state is 1111b as the CPU wrote
1110b into the status section of the CNSTAT register. After
the successful transmission, the buffer enters the TX_RTR
state and waits for a remote frame. When it receives a re-
mote frame, it will go back into the TX_ONCE_RTR state,
transmit its data bytes, and return to TX_RTR. If the CPU
writes 1010b into the buffer status section, it will only enter
the TX_RTR state, but it will not send its data bytes before
it waits for a remote frame. Figure 48 illustrates the possible
transmit buffer states.
! CAN error conditions
The receive/transmit interrupt access to every message
buffer can be individually enabled/disabled in the CIEN reg-
ister. The pending flags of the message buffer are located in
the CIPND register (read only) and can be cleared by reset-
ting the flags in the CICLR registers.
1100
TX request
CPU writes 1100
— Successful response to a remote frame. (Buffer state
— Transmit scheduling. (Buffer state changes from
— Detection of an CAN error. (The CEIPND bit in the
TX request
CPU writes 1110
the
changes from TX_ONCE_RTR to TX_RTR.)
TX_RTR to TX_ONCE_RTR.)
CIPND register will be set as well as the correspond-
ing bits in the error diagnostic register CEDIAG.)
CPU
CAN
schedules TX
configures
TX_NOT_ACTIVE
transmit failed
TX_BUSY0
1000
1101
TX done
Transmit
request cancelled
CPU writes 1000
DS042
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